r I/O Definition
MCLK 39 I/O Audio master clock for audio DAC.
TBCK 40 O A udio transmit bit clock.
SPDIF
41
OS/PDIF output.
SEL_PLL3IClock source select.
NC 42, 48 No connect pins. Leave open.
RSD45IAudio receive serial data.
RWS46IAudio receive frame sync.
RBCK 47 I A udio receive bit clock.
XIN 49 I C rystal input.
XOUT 50 O C rystal output.
AVEE 51 I A nalog power for PLL.
DMA[11:0] 66:61, 58:53 O DRAM address bus [11:0].
DCAS# 69 O DRAM column address strobe.
DOE# 70 O DRAM output enable.
DSCK_EN O DRAM clock enable.
DWE# 71 O DRAM write enable.
DRAS# 72 O DRAM row address strobe.
DMBS0 73 O S DRAM bank select 0.
DMBS1 74 O S DRAM bank select 1.
DB[15:0] 96:93, 90:85,
82:77
I/O DRAM data bus [15:0].
DCS[1:0]# 97,100 O SDRAM chip select [1:0].
DQM101 O D ata input/output mask.
DSCK 102OOutput clock to SDRAM.
DCLK105 I 2 7 MHz clock input to PLL.
YUV0
106
OYUV0 pixel output data.
CAMIN2 I C amera input 2.
UDAC O V ideo DAC output.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
SEL_PLL3 Clock Source
0Crystal oscillator
1 DCLK input
Mode YDAC
UDAC VDAC CDAC
AYCComposite C
BYCompositeComposite C
CYUComposite V
DYUCV
9-7
9-7
DVD PROCESSOR
ES6028F
DVD PROCESSOR
ES6028F
Name Number I/O Definition
YUV1 107OYUV1 pixel output data.
VREF I I nternal voltage reference to video DAC. Bypass to ground with 0.1 µF capacitor.
YUV2
108
OYUV2 pixel output data.
CDACOVideo DAC output. Refer to description and matrix for UDAC pin 106.
YUV3 109OYUV3 pixel output data.
COMP I C ompensation input. Bypass to ADVEE with 0.1 µF capacitor.
YUV4 110OYUV4 pixel output data.
RSET I D AC current adjustment resistor input.
ADVEE 111 I A nalog power for video DAC.
YUV5 113OYUV5 pixel output data.
YDAC O V ideo DAC output. Refer to description and matrix for UDAC pin 106.
YUV6 114OYUV6 pixel output data.
VDAC O V ideo DAC output. Refer to description and matrix for UDAC pin 106.
YUV7 115OYUV7 pixel output data.
CAMIN3 I C amera YUV 3.
PCLK2XSCN116 I/O 27-MHz video output pixel clock.
CAMIN4 I C amera YUV 4.
PCLKQSCN117 O 1 3.5-MHz video output pixel clock.
CAMIN5 I C amera YUV 5.
VSYNC# 118 I/O Vertical sync, active low.
CAMIN6 I C amera YUV 6.
HSYNC#
119 I/O Horizontal sync, active low.
CAMIN7 I C amera YUV 7.
HD[5:0]
127:122
I/O Host data I/O [5:0].
DCI[5:0] I/O DVD channel data I/O [5:0].
AUX1[5:0] I/O Aux1 data I/O [5:0].
HD[6]
128
I/O Host data I/O [6].
DCI[6] I/O DVD channel data I/O [6].
AUX1[6] I/O Aux1 data I/O [6].
VFD_DOUT I V FD data output.
HD[7]
131
I/O Host data I/O [7].
DCI[7] I/O DVD channel data I/O [7].
AUX1[7] I/O Aux1 data I/O [7:0].
VFD_DIN I VFD data input.
HD[8]
132
I/O Host data bus 8.
DCI_FDS# I/O DVD input sector start.
AUX2[0] I/O Aux2 data I/O 0.
VFD_CLK I VFD clock input.
HD[9]
133
I/O Host data bus line 9.
AUX2[1] I/O Aux2 data I/O [1] when selected.
SQSQ I S ubcode-Q data.
HD[10]
134
I/O Host data bus line10.
AUX2[2] I/O Aux2 data I/O [2] when selected.
SQSK I S ubcode-Q clock.
ES60x8 Pin Description (Continued)
Name Numbe
ES60x8 Pin Description (Continued)