div. table
19040_300_101110.eps
101110
Block diagram & Pinning information
TERMINAL
I/O/P DESCRIPTION
24-PIN
NAME
(PWP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
SD
2I
AVCC
RIN 6 I Audio input for right channel
LIN 5 I Audio input for left channel
GAIN0 18 IGain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCC
Mute signal for quick disable/enable of outputs (high = outputsswitch at50% duty cycle, low =
MUTE 4 I
outputs enabled). TTL logic levels with compliance to AVCC
BSL 21 I/O Boots
trap I/O for left channel
PVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
LOUT 22 O Class-D 1/2-H-bridge positive output for left channel
PGNDL 23, 24 P Power ground for left-channel H-bridge
VCLAMP 11 P Internally generated voltage supply for bootstrapcapacitors
BSR 16 I/O Bootstrap I/O for right channel
ROUT 15 O Class-D 1/2-H-bridge negative output for right channel
PGNDR 13, 14 P Power ground for right-channel H-bridge.
PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND 9 P Analog ground for digit
al/analog cells in core
AGND 8 PAnalog ground for analog cells in core
Reference for preamplifier inputs. Nominally equal to AVCC/8.Also controlsstart-up time via
BYPASS 7O
externalcapacitor sizing.
AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Connect to ground. Thermalpad should be soldered down on all applications to properly
Thermalpad Die padP
secure device to printed wiring b
oard.
LS
HS
OSC/RAMP
BYPASS
AVDDAVCC
(19, 20)
LIN
(5)
RIN
(6)
MUTE
(4)
BYPASS
(7)
GAIN1
(17)
GAIN0
(18)
SD
(2)
BSL
(21)
PVCCL
(1, 3)
LOUT
(22)
PGNDL
(23, 24)
VCLAMP
(11)
BSR
(16)
PVCCR
(10, 12)
ROUT
(15)
PGNDR
(13, 14)
VCLAMP
AVDD
AVDD
AVDD/ 2
AVDD
AVDD
AVDD/ 2
REGULATOR
AGND
(8, 9)
+
+
–
–
CONTROL
BIAS
THERMAL
MUTE
CONTROL
AV
CONTROL
SC
DETECT
SC
DETECT
LS
HS
VCLAMP