RADIOMETER TCM3 - Page 70

2. TCM3
Main PCB
Introduction
Three Versions
Micro-computer
TCM3 and TCM30 Service Manual
The Main PCB is CPU controlled and includes:
e
The
front
panel
control
for
the
display,
the
keys,
the
audio
transducer
and
the
electrode
holder
micro-switch.
+
The
serial
interface
for
the
digital
input-output/analog
output,
and
the
counting
*
system
for
the
pO./pCO,
and
heat
monitoring
channels.
ο 8 kbyte RAM and 56 kbyte program memory.
e Of particular importance is the electrode heating control function. Apart from
the software control, a hardware watchdog will switch off the heat if a software
error occurs.
The circuitry is shown on the drawings 2370-A1 and 3690-A2.
Please note that three versions of the Main PCB exist. The table below gives an
overview of the versions and their compatibility.
Part Used for Compatibility
901-643 TCM3 below R22 None
901-834 TCM3 from R22 onwards Hardware identical to 902-491
902-491 TCM30 Hardware identical to 901-834
The microcomputer consists of the CPU, QD1, the EPROMs QD9 and QD6, the
RAM QD8 and the address latch QD13.
A parity generator/controller (QD7, QD12 and QD26) uses the least significant bit
only. Where a parity error is detected, an NMI (interrupt) will be generated.
The addressing takes place via the address bus A8-A15 and the multiplexed
address/data bus AD0-AD7 and the address latch OD13.
The RESET-IN is activated at power-on and resets all peripherals with the
RESET-OUT signal.
If the NiCd battery voltage falls to below 6.5 volts, QASb pin 7 will go high,
cutting-off Q12. This will activate Q2, discharge C31 and reset the CPU. The
Power Save (PS) input is activated in order to let the CPU finish its current
instruction
cycle before being reset.
The CPU oscillator is driven by a 1.6 MHz crystal, setting the CLK to 0.8 MHz.
QD18 and QD17 are binary counters, producing the following internal timing
signals: 100 kHz clock for the Analog PCB, 163.84 and 655.36 ms reference
signals for the two A/D converters, 0.64 ms for the Bus Request (BREQ) signal
and 10.24 ms for the CPU interrupt RSTA (used for the “watchdog”).
Continued on next page