Reflex
Service
Manual Theory
of
Operation
The
interaipt
timer consists of
half
of
a
dual 4-bit
binary
counter
(U15),
one
section
of
a
Schmidt inverter
(U11),
and
one
half
of
a
flip
flop
(U13).
After
power-up, once the
Z80
is
running
and
U1 5
is released
from
reset,
it
will
count
16 high
to
low
WC/
transitions.
Transitions
occur every Lexichip-generated
word
clock period of
32|js.
Interrupts
to
the
Z80
occur every
51
2uS
with
a
low
pulse of
approximately 32uS. The
negative transition
of
this
pulse
triggers
the
interrupt. This interrupt
period offers ample time for
the Z80
to
perform
its
housekeeping and
critical
timing
related task without worrying
about
MIDI
IN
while in
the NMI
routine.
TheZ80
uses the
NMI/
to
service
the
timer
interrupt.
The NMI/
can
be
masked
(DISABLEINT/)
by
writing
a 0 to
pin
8
of
Output Register 2. DISABLEINT/ is
the
data
input for
the
flip-flop
(U13)
which
gets
clocked
by the WC counter to
generate
the
NMI/.
If
DISABLEINT/
=
0,
the
NMI/
signal
will
always
be
clocked through
as
HIGH
and the
NMI/ will never
be
asserted
at
the
Z80.
If DISABLEINT/
=
1,
the
NMI/
signal
will
get
clocked
as a
LOW
pulse of
approximately
32ps
as previously
desribed
. The
actual negative-going
edge
of this pulse triggers the interrupt.
NMI
behavior
on
Power
Up
In
the Interrupt
Timer
circuit, NMI/
is generated
from
a
flip-flop
whose
output
is
not predictable on power
up.
DISABLEINT/
(the D
input) is
set by
the
Z80
as soon
as it comes
out
of reset on power
up. After
this occurs, the
Z80
writes
to
the Lexichip
to
program
its word clock
as
an
output so that the interrupt timer
will
begin being clocked.
NMI/
is
at a
HIGH or
LOW
steady
state.
The Z80 NMI/
input is
negative
edge
triggered.
When the
Lexichip
is reset on
power-up,
the
chip
defaults
to
being
a slave
and attempts to
syncronize
its internal
word clock
to
any external
signal
on the WORD CLOCK
pin. The Z80
has
to
program
the
Lexichip
to
become
the
WC master.
When
the Lexichip
is
the word clock master,
it
drives
its
internal
word clock
out
on
WC/,
pin
59
of
U14.
The
Interrupt Timercannot
increment until
the Z80
tells the
Lexichip
to be
the
WC
master. Because the
Interrupt Timer
is not incrementing
on power-up,
NMI/
cannot occur.
This
is the normal
mode of operation.
Because
the interrupt
timer
counter
(U1
1)
gets
reset on power-up, the
first
time NMI/
can change
state
is
when
the
Qd 0/P
of the counter
goes
HIGH.
This
will
occur
after
8
WC/ are generated
after
power
up (256ps)
if
DISABLEINT/
is
set high.
INT/ CKT
(MIDI
IN)
The Z80
INT/
input is
dedicated
to
servicing MIDI IN. The RxRDY (UARTINT)
output
becomes
1
when the UART
receives one
character of
data
and
transfers
that
data
to
the receive
data
buffer;
that is,
when
the
data
can
be
read.
RxRDY
output is the same
as
bit 1 in
the status
register
which
is read
in the polling application.
NMI/ Circuit
(Interrupt Timer)
UARTINT
gets
inverted
by U1 1 to
generate
INT/ which
is tied
to
the
INT/
input
on the
Z80. When
the
Z80 gets reset
on power-up the
INT/
is disabled
by
default. This interaipt
must
be
software
enabled
before it can
used.
4-5
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