DEC.
1986
S-10
QUICK
DISK
SYSTEM
Data
transfer
between the
CPU and
the
disk is accom-
plished
through
the
QD
interface
consisting of 1C
USART
and IC31
QD
drive
interface
I/O.
QD^
hWIC30 USART
t
IC,31 QD
I'" 7
T
7
•
T
>
7
-
7
r
T
7
I/O/}'
b
ijJi;
T
I.
'i-T
USART
MB89251A
^
o
3
Q
o
s
-C
D
D
c/1
H
H
5
^
XDOOD^xoO
O-vjCDCJl-C^QDojN)
TOP
VIEW
O 3) O
3] O
X
<
DD
a
•<
CD
J)
cn
O
H
-<
H
X
^
in
^
«
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^
n
33
o
o
D
o
o
-*
PIN
NUMBER
PIN
NAME
1/0
DESCRIPTION
3
R.kD
!
(Receiver Data)
This
input is the
data read
from
QD
via IC31.
25
RxC
I
(Receiver Clock)
Controls
the
rate at
which the
data froK QD
is
received
tmmi b
^robco^S?
n ;
9
19
TxD
0
(Transmitter Data) This
output
is
to be
transmitted to QD.
QD^chjifir-^’
9
TxC I
(Trasmitter Clock)
Controls the rate at
which the data is
to
be
transmitted
to QD.
QD^cPciflT-^'
i;
PlfflSr 1:
n
•/
7
10
n
1
(Write)
A
"low" on this
input informs
the MB89251A that
the
CPU
is
writing data
or
controls to
the MB89251A.
CPUA>P>COWRITE®-t. LOWT
MB89251Ars«»Sa;(iorflg
cs I
(Chip Select) A
"low”
on
this input selects
the MB89251A.
rb'P/tSrra-h'L/ifl^.
L0Wi:'MB89251A*<-fe
P
7
hSill)
rB
1
(Read)
A
"low" on this
input informs the HB89251A
that the CPU
is
reading data or controls
from the MB89251A.
CPUA'PjtOREAOfi#
.
L0WT-MB89251A
A>
IffiE.
MM
RxRDY 0
(Receiver
Ready)
Not used
mm TxRDY 0
(Transmitter Ready)
Not used
m
SYNC
BRK
I/O (Sync Break)
Not used
n
CIS I
{
Clear to
Send Data)
Not
used. Pulled
low
LOW
o
TXEMP 0
(Transmitter Empty)
Not used
20
CK
!
(Clock) A clock of
3.25MHz
is
used
to
generate
internal
device
timing.
3
.
2 5
M H z
AT)
.
21
RST 1
(Reset) A "high"
on this
input
forces the MB89251A
into idle
mode.
HIGHT'RESET.
LOWT'Ji^ilff
.
22
0^ I
(Data Set Ready)
Used to
confirm
the position of the read/
write head. Should be
set to
low
only when
the
read/write
head is
positioning over a
read/write
sector.
qdot-s-v
Kea^M5/2*<7)AA.
0
(Request to Send) Not used
1
m
0
(Data Terminal Ready) A
"low" on this
ouptput is
used when
recording is performed
on
QD.
To
be inverted at IC31 output,
pin
25
WRGA.
QDt«J aUH^CLOW^aiA. DTRfs-tmC31(HB87013)F*lS«'f
7
J a
o
r
f y
25«
WRGAA‘
f,
QD
h'
7
d
A
t
JD i C.
fl
S
26
-
+
5
V
m
-
QD
DRIVE
INTERFACE
ADAPTER
MB87013
HMTSIMSMSMirHMlFHlMEIMM
m/2o333]ohQo
H
o
o
^
^
a
>
-a
H
=
H-IZ333)Z
cn^^^nxx
o
H
ro Q
”
o
a
PIN
NUMBER
PIN
.
NAME I/O
DESCRIPTION
1-6,
39,40
D7-D0 I/O Data Bus:
To
be
connected to the CPU data bus.
12
RST I
Reset; A
low
on this
input resets the MB87013.
0
-t
•:/
b
AAJST.
LOWTM B
8 7 0 1
3
ti
U
-t
/
b Sfll,
.
13
1
Read: Can be used to enable data
onto the data bus
from MB87013. Active
low.
M B
8
7
0 1 T^r
T
y.
O-cO
14
WR
1
Write: Used to write data into the MB87013
register.
Active low.
M B
8
7
0 1
T
7
-f
t r.
o-(7)
11
1
Chip
WR.
^
'•/
7
M B
^
CS
Selec
AO anc
-fe y
7
0
A1
t:
Can
A1 to
7
bA
30P
AO
be us
gain
/DbT
RD
ed in
access
.
hT)
yX9''
WR
conjunction
with
a
low RD, low
to internal registers.
.
w"r, AO, All:
DATA BUS
OCS
1
- - - -
Hi-imp
1
0
0
0 0
1
Hi-imp
0
0 0 0 1
0
Data
Register Write
0
(MB89251A.MB87013)
0 0
1 0 1
Hi-imp 0
0
0 1 1
0
Hi-imp 0
0 1 0 0 1
CRC Register (MSB) Read
1
0
1
m
1
0
Data
Register Write
1
0
m
0
1
Control Register Read
i
CRC Register (LSB) Read
0
rv
nr 1
0
Control
Register Write
1
8
9
AO
A1
!
Address: Used
to
select internal register,
g:
Ia
xX
it
^
,
IH
INIT
0
Reset output: Inverted RST.
Active
high.
RST^R|£t:^cr7xT
/HIGHco-J-ir-y
B
inTb
0
Low active
reset output:
Buffered RST.
RST^7':v7r
'j
T
LOWcrj'J'fe
"/
29
ocs
0
Chip Select: Used to select
serial interface(MB89251A).
yy
T/b.-T
y3'
—
7x-7.MB89251A(/)CS(l^.
(0CS=CS+A1)
33
TxD
I
Transmitter Data: To be
re-transmi tted to QD after modified
frequency modulated.
34
TxC 0
Transmitter Clock: Controls
the rate at
which
data is
transmitted to
QD
drive,
jSfl[5]ffl7
a
/
7
37
RxD
0
Receiver Data: Demodulated data read
from
QD. To be
re-
transmitted to
IC30.
gftT-7aiA5S?.
36
RxC 0
Receiver Clock:
Controls the rate at which 1C30 receives
the data from QD
via
IC31.
Sl|a]Bfi7n.v7tilAS^.
1
Gate: A
low on this input enables
transfer of data read from
QD to 1C30.
through RxC and RxD.
gflr-^S-,
R X C
i;
RxD(Citiyi-r«,B#coy- b
.
LOW
t'»(lT-7$:MB 8
9
2
5 1
it'KicjS-C'#
.
B
DTR I
A
low
on this
input causes MFM modulator
to
be
initialized.
26
WRDT 0
Data out:
Signal from this output is to be
recorded on QD.
24
RDT I
Data In:
Data read from QD is
received through this port.
7
T
-y
7
r
T
7
7 U
-
25
WRGA 0 A high
from this
output enables recording on QD.
7T
:/
7r
/
77(iWRG
A*''H
I
G
HCOD#,
t -f
7
7
tC
t-
7
AUH*.!..
G£0S|AtmDTR7)R|Ea*sit!7i$ixS.
27
IPO
I
Indicates the
status
of
the
WRITE
PROTECT
switch:
With a disk
inserted a high IPO
represents"WRITE PROTECTED".
praf-:?
QD
T\
H I
23
IPl 1
Used
to sense
QD:
Low=QD inserted. High=QD not
inserted.
22
IP2
QDcoffy.,
f*a;ffl-+r-b.
L
=
ffA,
h
=
a#a
18
0P3
0 Used
to turn on/off disk
unit motor: Low=0N.
^“7cOON-OFFt'-yP. LOWT'ON
17
0P4
0 This
output is connected to
RTS. Low 0P4 enables
MB89251A
to
recieve data from QD.
RTS^7>-Fd-/L„
LOWT^fl^lg.
20
XTAL
6.5MHz crystal
input for internal
oscillator.
6.
5MH
21
EXAL
Not used
30
VDD
Main power supply:
+5V
+
5
V
10
vss
Circuit GND
potential
G N D
31
TST
Used for test
purpose only: must
be pulled up
to
VDD.
ISVD DtC7-;LT 'yr.
9
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