Samsung NP R40 - Page 51

Samsung
Confidential
CLK.
LVDS I/F
4 OF 5
SVID
DACCRT
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
B
3
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
ELECTRONICS
3
D
SAMSUNG ELECTRONICS CO’S PROPERTY.
A
4
EXCEPT AS AUTHORIZED BY SAMSUNG.
resistor on this strap to separate it from the I2C circuit during an NB reset
C
Debug strap configuration. This strap should not be set to "0" on production boards.
decoupling CAPS on the botom side close to BALLS
12
THIS DOCUMENT CONTAINS CONFIDENTIAL
12
0 : Reserved
PROPRIETARY INFORMATION THAT IS
THIS DOCUMENT CONTAINS CONFIDENTIAL
C
A
D
3
SAMSUNG PROPRIETARY
SAMSUNG
DACVSYNC
0 : Enable integrated graphics
D
0 : DDR3. On DDR3, it is necessary to put an isolation FET in series with the pull-up
1 : Disable integrated graphics
3
SAMSUNG ELECTRONICS CO’S PROPERTY.
B
P3.3V_NB CONTROL CIRCUIT
C
B
4
DACHSYNC
C
Select configuration of the integrated graphics engine.
1 : DDR2
Enable/Disable integrated graphics.
A
STRAP PIN
0 : Select Memory Channel A to be a debug bus
DESCRIPTION
DDC_DATA
1 : Read debug straps from an external EEPROM, or disable debug mode when an EEPROM is absent.
B
4
2
A
1 : Required setting for the RS600M
EXCEPT AS AUTHORIZED BY SAMSUNG.
Put the AVDD,AVDDI,AVDDQ,PLVDD
Select DDR2 or DDR3 signalling level for the memory interface.
2
SAMSUNG PROPRIETARY
STRP_DATA
CLOSE TO CRT CONN
D
PROPRIETARY INFORMATION THAT IS
1
STRAP DEFINITIONS FOR THE RS600M
4
1
R99
4.7K
P1.8V
33K
26-C3
C151
4700nF
R131
B18
BLM18PG181SN1
nostuff
6.3V
10V
C101
2200nF
6.3V
C99
4700nF
P3.3V_NB
nostuff
P3.3V_NB
10V
2200nF
C102
P5.0V_ALW
nostuff
6.3V
C146
4700nF
3
2
nostuff
4700nF
C103
6.3V
27-A2
BAV99LT1
D12
nostuff
1
27-A3
51-C3
BLM18PG181SN1
B12
51-B4
26-C4
B5
BLM18PG181SN1
26-C3
C148
100nF
AVDDQ
P3.3V_NB
2200nF
C147
10V
4.7K
R104
100nF
C100
26-C4
P1.8V
P3.3V_NB
nostuff
B10
BLM18PG181SN1
B6
BLM18PG181SN1
R110
0
50-D4 27-C2
27-C250-D4
AVDD
50-D18-B1
26-C3
26-C4
10V
2200nF
C144
2200nF
C104
10V
10V
C134
2200nF
26-C3
Q24
RHU002N06
3
D
G
1
S
2
BLM18PG181SN1
B9
P3.3V_NB
4.7K
R96
51-D2 27-B2
27-B3 51-B4
50-B1 26-D2 26-B4
26-B451-C2
100nF
C145
1%
R127
150
26-C4
SI2315BDS-T1
Q25
D
3
1
G
2
S
nostuff
P1.2V
P1.8V
P3.3V
R102
4.7K
P1.8V
16V
C153
470nF
10V
2200nF
C175
B7
BLM18PG181SN1
B11
BLM18PG181SN1
1%
R124
150
8-C1
51-C2 26-C4
P1.2V
1%
R101
681
50-D227-C4
27-D4 50-C1
8-C1
150
R123
1%
R109
0
nostuff
P1.8V
B18
VDDR3_2
A30
VSSLT_1
A26
VSSLT_2
C29
VSSLT_3
F24
VSSLT_4
V12
VSSPLL_PCIE_1
T12
VSSPLL_PCIE_2
T13
VSSPLL_PCIE_3
F18
Y
TXOUTU2P_RESERVED
E23
TXOUTU3N_RESERVED
F23
TXOUTU3P_RESERVED
H24
VDDLT18_1
J24
VDDLT18_2
J23
VDDLT33_1
H23
VDDLT33_2
M10
VDDPLL_PCIE_1
P13
VDDPLL_PCIE_2
P12
VDDPLL_PCIE_3
A18
VDDR3_1
B30
TXOUTL1P_RESERVED
B29
TXOUTL2N_RESERVED
A29
TXOUTL2P_RESERVED
C28
TXOUTL3N_RESERVED
C27
TXOUTL3P_RESERVED
C24
TXOUTU0N_RESERVED
C25
TXOUTU0P_RESERVED
D24
TXOUTU1N_RESERVED
E24
TXOUTU1P_RESERVED
H21
TXOUTU2N_RESERVED
J21
SMB_CLK
B22
SMB_DATA
B14
STRAP_DATA
B26
TMDS_HPD
A27
TXCLKLN_RESERVED
B27
TXCLKLP_RESERVED
E21
TXCLKUN_RESERVED
F21
TXCLKUP_RESERVED
B28
TXOUTL0N_RESERVED
A28
TXOUTL0P_RESERVED
C30
TXOUTL1N_RESERVED
GPIO2_LVDSBLON
D3
GPIO3_LVDSDIGON
C5
GPIO4_LVDSENABL
F19
GREEN
B21
LTPVDD18
A21
LTPVSS18
B11
OSCIN
A12
PLLVDD12
A14
PLLVDD18
A11
PLLVSS
D19
RED
C21J19
BLUE
D18
COMP_PB
B7
CPU_CLKN
A7
CPU_CLKP
J18
C_PR
B24
DACHSYNC
B23
DACVSYNC
A25
DAC_RSET
A22
DAC_SDA
B12
DDC_DATA
C4
U507-4
RS600ME
B19
AVDDDI
A23
AVDDQ
A17
AVDD_1
B17
AVDD_2
A19
AVSSDI
M23
AVSSN_1
N23
AVSSN_2
A24
AVSSQ
P1.8V
Q30
MMBT3904
1
3
2
P3.3V_NB
10V
C150
2200nF
R103
4.7K
50-C427-D4
BLM18PG181SN1
B8
R108
33
2200nF
C176
10V
1%
R126
150
PLLVDD18
R132
10K
1%
R125
150
P1.8VP3.3V_NB
2200nF
C135
10V
LCD1_ADATA2
LCD1_ADATA2#
LCD1_ADATA1
LCD1_ADATA1#
LCD1_ADATA0
LCD1_ADATA0#
CRT3_DDCDATA
LCD3_VDDEN
LCD3_BKLTEN
VGA3_VSYNC
VGA3_HSYNC
LCD1_ACLK
LCD3_BKLTCTRL
CRT3_DDCCLK
CLK0_HCLK1
LCD1_ACLK#
TVO3_C
TVO3_Y
CRT3_BLUE
CRT3_GREEN
CRT3_RED
CLK3_NB14M
CLK0_HCLK1#