Samsung R730 - Clock Distribution

8-6
R530/R730
8. Block Diagram and Schematic
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
CLK1_MCLK4/4# CLK1_MCLK0/0# CLK1_MCLK1/1#
SODIMM #0
SODIMM #1
333/400 MHz
266 MHz
CLK0_HCLK/CLK#
266 MHz
10 MHz
Page 8
MCH3_CLKREQ#
CLK1_DREFSSCLK/DREFSSCLK#
100 MHz (SRC 6)
1
SPI
KBC3_SPI_CLK
17.86 MHz
HPLL
xSLG8SP513r05)
100 MHz
CLK1_DREFCLK/DREFCLK#
96 MHz
CLK1_PCIEICH/PCIEICH#100 MHz (SRC 3)
CLK1_PCIELOM/PCIELOM#100 MHz (SRC 9)
32.768 KHz
PCI Express Gfx
100 MHz (SRC0)
OSC
HD Audio
WIRED LAN
LOM3_CLKREQ*#
CLK3_USB4848 MHz CLK1_SATA/SATA#
100 MHz (SRC 2)
CLOCK DISTRIBUTION
667/800 MHz
CLK1_MCLK3/3#
CLK3_PCLKICH33 MHz
33 MHz CLK3_PCLKMICOM
BSEL
14 MHz
OSC
Main PLL
SSC
48MHz PLL
CLK0_HCLK1/HCLK1#
CLK1_DREFSSCCLK/DREFSSCCLK#
#LLP
G
3
H
C
M
/L
LP
G
3
H
C
M
_1KL
C
)4CRS
(
z
H
M
0
01
AUD3_BCLK
CPU
MCH
KBC
14.318 MHz
CK-505M (w/ CLKREQ* & SSDC)
FS(2:0)
CPU_STP*
ITP_EN
SS(96/100) SEL
PCI_STP*
P3.3V
CLK3_PWRGD*
100 MHz (SRC 6,9)
WLAN
CLK1_MINIPCIE/MINIPCIE#
RTC Clock
25 MHz
333/400 MHz
A
A
SAMSUNG
2
OF
3
B
C
2
PCIE PLL
DPLLA
MPLL
DPLLB
ICH9-M
USBPLL
SATAPLL
32.768 KHz
PCIEPLL
Cantiga
3
PART NO.
PAGE
DATE
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
CHECK
B
LAST EDIT REV
14.318 MHz
CHP3_SATACLKREQ#
Jun PARK
4
THIS DOCUMENT CONTAINS CONFIDENTIAL
1
D
D
C
4
ELECTRONICS
1
PLL3
SSC
33 MHz
Buffer
MUX
MUX
MUX
FSB
PEG
DMI
DEV. STEP
SAMSUNG ELECTRONICS CO’S PROPERTY.
TITLE
MODULE CODE
EXCEPT AS AUTHORIZED BY SAMSUNG.
APPROVAL
SAMSUNG PROPRIETARY
PROPRIETARY INFORMATION THAT IS
DRAW
MIN3_CLKREQ*#
333/400 MHz 333/400 MHz
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN
CLOCK DIAGRAM
MAIN
Bremen-L
596
BA41-xxxxxA
October 27, 2009 14:27:43 PM
1.0
PV
9/23/2008
undefined
HJ.KIM
YM.AHN