Sanyo CP10 - IC Block Diagrams: Memory and Microcomputer; RAM and Microcomputer IC Details

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1C BLOCK DIAGRAM
O
|Time
constant
switching
output
for
DBOG
1/0
|
Data
pin
of
external
RAM.
DATA
6
spindle
motor
output
filter.
DBO5}
[/O}
Data
pin
of
external
RAM.
DATA
5
O
|ON/OFF
control
output
for
spindle
33
|
VDD
—
|
Power
supply
(+5
V)
motor.
34
|
DBO4|
1/0}
Data
pin
of
external
RAM.
DATA
4
O
/|Spindle
motor
drive
output.
Rough
35}
DBO3
1/0
|
Data
pin
of
external
RAM,
DATA
3
control
for
CLV—S
mode
and
phase
36
|
DBO2
1/0
|
Data
pin
of
external
RAM,
DATA
2
control
for
CLV—P
mode.
37
|
DBO1
1/0
|
Data
pin
of
external
RAM,
DATA
1
O
|Drive
output
for
spindle
motor.
Speed
(LSB)
control
for
CLV—P
mode.
38
|
RAO!
O
|
Address
output
of
external
RAM.
|
|
EFM
signal
input
from
RF
amplifier.
ADDRO1
(LSB)
O
|Output
for
controlling
slice
level
of
39}
RAOQ2
O
|
Address
output
of
external
RAM,
EFM
signal.
ADDROQ2
|
|MIRROR
input
from
RF
amplifier.
40
|
RAO3
O
|
Address
output
of
external
RAM,
O
|
VCO
output.
When
output
is
locked
to
ADDRO3
EFM
sj
=
MH
signal,
8.6436
.
.41
|
RAO4
O
|
Address
output
of
external
RAM,
1
|
VCO
input.
1
ltovy
ADDR0O4
:
42}
RAOS|
O
|
Address
output
of
external
RAM,
O
|Phase
comparison
output
between
EFM
ADDRO05
ignal
and
VCO/2.
_
pats
ae
43
|
RAOG6
OQ
|
Address
output
of
external
RAM.
1
|
Serial
data
transfer
clock
input
from
ADDRO6
;
ee
a
44
|
RAO7
O
|
Address
output
of
external
RAM.
CPU.
Data
is
latched
at
rising
edge
of
Binal
ADDRO7
.
RA
A
M
|
|
Latch
input
from
CPU,
Data
in
8~bit
aia
O81.
SO
ce
preteen
if
:
Bot
eta
CPU)
j
elite
es
ade
(serial
cael
oe
46
|
RAOQ
O
|
Address
output
of
external
RAM,
latched
in
each
register.
R
|
|
Serial
data
input
from
CPU
panei
:
ope
47
|
RA10
O
|
Address
output
of
external
RAM,
|
|
System
reset
input.
The
system
is
reset
ADDRO10
i
i
LOW
:
|
ae
shat
F
IeNe
48
|
RA11
O
|
Address
output
of
external
RAM,
Gods
nanan
din
ADPROt1
(MSE)
EU
ie
pargia
ey
Pellesre
9
49}
RAWE!
O
|Write
Enable
signal
output
to
external
to-adidtess:
RAM.
(active
at
LOW
level)
1
|
Muting
input.
When
ATTM
of
internal
a.
;
,
.
:
:
50
|
RACS
O
|
Chip
Select
signal
output
to
external
register
A
is
at
LOW
level,
MUTG
is
at
:
COW
level
sade
oe
RAM.
(active
at
LOW
level)
.
Se
pee
Bigy
eh
Te
eB
NOLS
51
|
C4M
O
|
1/2
frequency-divided
output
of
X'‘tal,
condition.
When
these
statuses
are
f=5.2336
MHz
HIGH
level,
no
sound
is
output.
p
O
|
Outputs
result
of
CRC
check
of
sub-
ea
aac
Fa
ca
es
en
ene
a
53
|
XTA1
{|
X'tal
oscillator
circuit
input.
|
1
Clock
gue
for
serially
outputting
sub-
i
836¢2
Ne
om
y
P
XTAP
O
|
X'tal
oscillator
circuit
output.
ns
f=8.4762
MHz
O
{Serial
output
of
sub-code.
:
55
|
C2FL
O
|
Correction
status
output.
Becomes
O
|Sub-code
O
output.
‘
NNH”
when
C2
system
presently
O
|Sub-code
sync
SO
+
$1
output.
:
O
|Write
Fr
Plocksuiman
Whehhame
being
corrected
cannot
be
corrected.
‘
ame
a
ou
Sn
3
56
|
C2PO
O
Display
output
of
C2
pointer.
;
he
esha
f
=7.35
kHz.
ig,
Synchronized
with
audio
output,
;
ead
ee
lock
output.
7.3
2
|
57
|
RAOV|
O
[Display
output
of
overflow
and
under-
6
Bs
i
ere
;
|
low
of
+4
frame
jitter
absorbing
RAM,
SPAY
CULE
OT
IaIne-Sy
NG
REOTREHOA
58
|
SLOB
I
ode
switching
input
of
audio
data
6
oe
i
feo
output.
It
is
complement
output
at
isplay
output
of
frame
sync
loc
LOW
level
and
offset
binary
output
at
1/0
Dae
f
RAM,
DATA
8
palates
san
Bkexteinat
:
59
|
PSSL
1
Mode
switching
input
of
audio
data
;
tput.
It
is
serial
output
at
LOW
level
10
|D
RAM,
DATA
ae
/
ata
pin
of
external
.D
1
|
Five
parallllel
cutpueae
HIGH
level:
—18—
|