Sanyo CP10 - IC Block Diagrams: Data Interface Pins; Audio Data and Interface Pinouts

IC BLOCK DIAGRAM
Power supply (+5 V)
~19—
Vo
Function
Vo
Function
O
|
Aperture
compensation
control
output.
O
|
DA12
output
when
PSSL
js
at
HIGH
It
is
HIGH
level
for
R—channel
level.
DENL
is
output
when
PSSL
is
at
correction.
LOW
level.
O
|
Aperture
compensation
contro!
output.
O
|
DA13
output
when
PSSL
is
at
HIGH
it
is
at
HIGH
fevel
L—channel
level.
DENR
js
output
when
PSSL
is
at
correction.
LOW
level.
O
|
DAO?
(LSB
of
parallel
audio
data)
is
O
|
DA14
output
when
PSSL
is
at
HIGH
output
when
PSSL
is
at
HIGH
level.
level.
C210
is
output
when
PSSL
is
at
C1F1
is
output
when
PSSL
is
at
LOW
LOW
level.
level.
O
|
DA15
output
when
PSSL
is
at
HIGH
O
|
DAO2
is
output
when
PSSL
is
at
HIGH
level.
C210
is
output
when
PSSL
is
at
level.
C1F2
is
output
when
PSSL
is
at
LOW
level.
LOW
level.
O
|
DA16
(parallel
audio
data
MSB)
output
O
|
DAO3
is
output
when
PSSL
is
at
HIGH
when
PSSL
is
at
HIGH
level,
DATA
level.
2F
1
is
output
when
PSSL
is
at
output
when
PSSL
is
at
LOW
level.
LOW
level.
O
|
88.2
kHz
strobe
signal
output.
O
|
DA0O4
is
output
when
PSSL
is
at
O
|
44.1
kHz
strobe
signal
output.
HIGH
level.
C2F2
is
output
when
aa)
PSSL
is
at
LOW
level.
O
|
DAOS
output
when
PSSL
is
at
HIGH
level.
UGFS
is
output
when
PSSL
is
at
LOW
level.
Note:
O
|
DAO6
output
when
PSSL
is
at
HIGH
1/0:
Input/Output
level.
WFCK
is
output
when
PSSL
is
at
C1F1&C2F2:
Monitor
output
of
error
correction
LOW
level.
status
during
C1
decoding.
O
|
DAO7
output
when
PSSL
is
at
HIGH
C2F1&C2F2:
Monitor
output
of
error
correction
level.
FCKV
is
output
when
PSSL
is
at
status
during
C2
decoding.
LOW
level.
UGFS:
Output
of
non-protected
frame
sync
O
|
DAO8
output
when
PSSL
is
at
HIGH
pattern.
level.
FCKX
is
output
when
PSSL
is
at
WFCK:
Inverting
output
of
WFCK,
LOW
level.
FCKV:
Outputs
WFCK/4
or
WFCK/8.
O
|
DA10
output
when
PSSL
is
at
HIGH
FCKX:
Outputs
RFCK/4
or
RFCK/8.
level.
PLCK
is
output
when
PSSL
is
at
PLCK:
VCO/2
output.
When
output
locks
onto
LOW
level.
EFM
signal,
f=4,.3218
MHz
O
|
DA10
output
when
PSSL
is
at
HIGH
C4LR:
176.4
kHz
strobe
signal.
level. LRCK
is
output
when
PSSL
is
at
DENL/DENR:
Enable
signal
of
serial
data
of
L—ch.
LOW
level.
Enable
signal
of
serial
data
of
R—ch.
O
|
DA11
output
when
PSSL
is
at
HIGH
C210/C210:
—
Bit
clock
output.
f=2.1168
MHz.
level.
C4LR
is
output
when
PSSL
is
at
Inverted
signal
of
/C210.
LOW
level.
DATA:
Serial
data
output
of
audio
signal.