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General Purpos e I/O (Host Interface) (3 pins).
134
GPAIO
3-S I/O (r.t.) Reset: input
Standby: 3-S
General purpose input/output pin, monitored/controlled by the audio processor software. After RESET, this pin is defined
as input. Its definition can be configured through ADP commands.
145
GPSI
I I Input
General purpose input, monitored by the system de-multiplexer/video processor software.
143
GPSO
O O (p.d.) Reset: output (low)
Standby: 3-S
General purpose output, controlled by the system de-multiplexer/video processor software. After RESET it outputs a low
level.
DVD-DSP Interface (13 pins).
151
DVDREQ
O O (p.d.) Reset: output (low)
Standby: 3-S
DVD-DSP data request output (programmable polarity).
149
DVDVALID
I I Input
DVD-DSP data valid input (programmable polarity).
148
DVDSOS
I I Input
DVD-DSP start of sector input (programmable polarity).
159
158
157
156
155
154
153
152
DVDDAT
[7]
DVDDAT
[6]
DVDDAT
[5]
DVDDAT
[4]
DVDDAT
[3]
DVDDAT
[2]
DVDDAT
[1]
DVDDAT
[0]
I I Input
DVD-DSP data input bus.
150
DVDSTRB
I I Input
DVD-DSP data bit strobe (clock) input. Programmable polarity.
147
DVDERR
I I Input
DVD-DSP error indication input. Programmable polarity.
CD-DSP Interface (4 pins).
5
6
7
8
CDERR
CDFRM
CDDAT
CDCLK
I
I
I
I
I/O (r.t.)
I/O (r.t.)
I/O (r.t.)
I/O (r.t.)
Reset: input (p.d.)
Standby: 3-S (p.d.)
When
HWID
is connected to GNDP, these are the CD-DSP I
2
S input port pins as follows:
CDERR
: data error indication input
CDFRM
: left/right channel frame input
CDDAT
: data input
CDCLK
: bit clock input
When
HWID
is connected to VDDP, these are
HD
[15:12] of the host data bus, as explained in the host interface pin
description.
Pin Name Ty pe Direct io n
Status After RESET/
During STANDBY
Digital Audi o Interface (8 pins).
131
AMCLK
3-S I/O (p.u.) Reset: input
Standby: 3-S
Audio Master Clock input/output. 128, 192, 256, 384 or 512 times the sampling frequency (programmable).
133
S/PDIF
(
AOUT
[3]) O O (p.d.) Reset: input
Standby: 3-S
S/PDIF transmitter output for digital coded or reconstructed audio data. Alternately can be used as a fourth audio output.
After RESET this pin outputs low level.
138
137
136
AOUT
[2]
AOUT
[1]
AOUT
[0]
O O (p.d.) Reset: output (low)
Standby: 3-S
Serial outputs of digital stereo audio.
113
AIN
I I Input
Serial input of digital stereo audio.
139
ALRCLK
O O (p.d.) Reset: output (low)
Standby: 3-S
Digital audio left/right select output for the audio port. Square wave, at the sampling frequency. Programmable polarity
interpretation for input.
141
ABCL K
O O (p.d.) Reset: output (low)
Standby: 3-S
Digital audio bit-clock output. Data on
AOUT
and
AIN
is output or latched, respectively, with the rising or falling
(programmable) edge of this clock.
PLL/Clock In terface (5 pins).
120
GCLK
I I Input
27.000MHz clock or crystal input for main processing clock generation.
117
GCLK1
I I Input
27.000MHz clock input for audio master clock generation. In normal operation must be connected to
GCLK
.
119
XO
OAO
Output to a crystal that is connected to
GCLK
. If a crystal is not used at
GCLK
,
XO
must be left not connected.
115
118
PLLCFG
[1]
PLLCFG
[0]
I
I
I
I
Input
Input
PLL configuration inputs. Allowed to be changed only during RESET. In normal operation both pins must be connected to
GNDP.
Pin Name Type Direct ion
Status After RESET/
During ST
ANDBY
IC BLOCK DIAGRAM & DESCRIPTION
IC820 ZR36732 (MPEG)
17
18
20
21
22
23
24
25
HD
[7]
HD
[6]
HD
[5]
HD
[4]
HD
[3]
HD
[2]
HD
[1]
HD
[0]
3-S
3-S
3-S
3-S
3-S
3-S
3-S
3-S
I/O (r.t.)
I/O (r.t.)
I/O (r.t.)
I/O (r.t.)
I/O (p.u.)
I/O (r.t.)
I/O (r.t.)
I/O (p.u.)
Reset: input (p.d.)
Standby: 3-S (p.d.)
For 16 bits mode, the 8 l.s. data lines of host data bus. For 8 bits mode, only these signals are defined as host data
signals.
9
11
13
15
HD
[11]
HD
[10]
HD
[9]
HD
[8]
3-S I/O (p.d.)
I/O (r.t.)
I/O (r.t.)
I/O (r.t.)
Reset: input (p.d.)
Standby: 3-S (p.d.)
When
HWID
is connected to VDDP, these are data lines 11:8 of the 16-bit host data bus.
5
6
7
8
HD
[15]
HD
[14]
HD
[13]
HD
[12]
3-S I/O (r.t.)
I/O (r.t.)
I/O (r.t.)
I/O (r.t.)
Reset: input (p.d.)
Standby: 3-S (p.d.)
When
HWID
is connected to VDDP, these are data lines 15:12 of the 16-bit host data bus. When
HWID
is connected to
GNDP, these are the CD-DSP I
2
S input port pins, as explained in the CD-DSP pin description.
27
28
29
30
HA
[3]
HA
[2]
HA
[1]
HA
[0]
I
I
I
I
I
I
I
I
Input
Host address inputs. These input signals indicate the register accessed in every cycle on the host interface.
32
HCS#
I I Input
Host chip-select input.
31
HWR#
ó
HR/W#
I I Input
In host protocol Type A (
HTYPE
= GNDP):
HR/W#
. This input determines the direction of the host access.
In host protocol Type B (
HTYPE
= VDDP):
HWR#
. Host write input.
34
HRD#
ó
HDS#
I I Input
In host protocol Type A (
HTYPE
= GNDP):
HDS#
. Data strobe input (active low).
In host protocol Type B (
HTYPE
= VDDP):
HRD#
. Host read input (active low.)
36
HRDY
3-S O (p.d.) Reset: output (low)
Standby: 3-S
Host ready output. When this signal is tri-stated (i.e., it requires a pull-up resistor), up to
SysConfig.CodBurstLen
bytes of
code can be written to the Decoder with no need to poll its condition in between. When
HRDY
is low during a host
access, the Decoder may still receive at least two additional bytes of code without corrupting the data.
37
HIRQ#
3-S O (p.u.) 3-S (p.u.)
Interrupt request. This output signal requests an interrupt from the host controller, if one of the events associated to
interrupts occurs, and it is not masked-off. It is de-asserted if the host responds to the interrupt by reading the interrupt
status register, or if the host disables the interrupt, or after RESET.
Deassertion of the
HIRQ#
output has two modes: De-activated and then tri-stated or directly to is a tri-state condition.
The pin needs external pull-up resistor.
39
HACK#
3-S O (p.u.) Reset: output (high)
Standby: 3-S (p.u.)
Host acknowledge output. In protocol A, the Decoder indicates that a read or write cycle is completed by asserting this
output. In protocol B, this signal is used by the Decoder to indicate a wait state that may be used by fast hosts. In protocol
B the host may ignore the
HACK#
signal.
When this signal is deasserted it is de-activated and then tri-stated. This pin needs an external pull-up resistor.
Pin Name Typ e Direct io n
Status After RESET/
During ST
ANDBY
Video Syncs and Clocks Interface (5 pins).
127
VCLK
X
2
3-S O (r.t.) Reset:
Standby: 3-S (p.d.)
Main video clock. 27.000MHz.
92
VCLK
3-S O (r.t.) Reset:
Standby: 3-S (p.d.)
A division by two of the
VCLK
X
2
signal. This signal is used as a sync qualifier.
95
HSYNC
3-S O (r.t.) Reset:
Standby: 3-S (p.d.)
Horizontal sync. Polarity and duration are programmable.
93
VSYNC
3-S O (r.t.) Reset:
Standby: 3-S (p.d.)
Vertical sync. Polarity and duration are programmable.
96
FI
3-S O (r.t.) Reset:
Standby: 3-S (p.d.)
Field indication. Polarity is programmable.
Analog Video Encoder Interface (7 pins).
102
CVBS/G/Y
(DAC A)
OAO Reset:
Standby: 3-S
When the Decoder outputs composite video, this line is CVBS
When the Decoder outputs RGB, this line is the Green output
When the Decoder outputs YUV, this line is the Y output
105
Y/R/V
(DAC B)
OAO Reset:
Standby: 3-S
When the Decoder outputs the composite video, this line is Y
When the Decoder outputs RGB, this line is the Red output
When the Decoder outputs YUV, this line is the V output
106
C/B/U
(DAC C)
OAO Reset:
Standby: 3-S
When the Decoder outputs the composite video, this line is C
When the Decoder outputs RGB, this line is the Blue output
When the Decoder outputs YUV, this line is the U output
103
CVBS/C
(DAC D)
OAO Reset:
Standby: 3-S
When the Decoder outputs any of the types of video, this line can be programmed to output either composite or C.
108
RSET
IAI
Resistive load for gain adjustment of the DACs
111
VREF
IAI
Voltage reference for gain adjustment of the DACs
100
COSYNC
3-S O (p.d.) Reset: output (low)
Standby: 3-S
Composite sync output. Active only when RGB analog output is selected. Otherwise, the signal is low.
Pin Name Type Directio n
Status After RESET/
During ST
ANDBY
Pin Name Typ e Direct io n
Status After RESET/
During STANDBY
Reset, Standby and Idle Status Interface (3 pins)
124
RESET#
I I Input
Reset input. Once de-asserted, the Decoder starts the initialization process.
122
STNDBY#
I I Input
Stand-by input. When asserted together with
RESET#
, all outputs and bidirectional pins float, such that the Decoder is
electrically disconnected from its surroundings. All internal clocks are disabled, and the power consumption is minimized.
160
IDLE
3-S O (p.u.) Reset: output (high)
Standby: 3-S (p.u.)
Idle, Init and Reset states indication output.
Host Interface (29 pins)
2
HWID
I I Input
Determines the width of the host interface data bus. It is allowed to be changed only during RESET. A low level (GNDP)
configures the Decoder to an 8-bit host data interface, a high level (VDDP) to 16-bit width.
1
HORD
I I Input
Determines the order of bytes on the host interface data bus in case of 16-bit width (
HWID
at VDDP). It is allowed to be
changed only during RESET. A low level (GNDP) configures the Decoder to input/output the m.s. byte on
HD
[15:8], a
high level (VDDP) to input/output the m.s. byte on
HD
[7:0]. Must be at GNDP if the host data bus is 8 bits.
4
HTYPE
I I Input
Determines the protocol type for the 8 and 16 bits modes host interface. It is allowed to be changed only during RESET.
A low level (GNDP) configures the Decoder to type A, a high level (VDDP) to type B
.
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