R/W Buf.
Micon interface
ALU
78
76
77
68 67 66 65 64 63 62 61 60 59 58 55
X
SS
XI
XO
80
XV
DD
81
DV
SR
82
RO
83
DV
RR
84
DV
DD
85
DV
RL
86
LO
87
DV
SL
VDD
VSS
93
MXO
94
MXI
24
P1-3
21
P1-0
92
INTR
32
P4-3(SCK/SCL)
31
P4-2(S10/S11/SDA)
30
P4-1(S12)
29
P4-0(ADin/BUZR)
28
P3-3(ADin3)
27
P3-2(ADin2)
26
P3-1(ADin1)
25
P3-0
Bias
LCD Driver/Output Port Port 8
Port 2
Power on Reset
COM1(OT1)
9897
COM2(OT2)
99
COM3(OT3)
10 0
COM4(OT4)
1
S1(OT5)
2
S2(OT6)
10
S10(OT14/ZDET)
11
S11(OT15/CLCK)
12
S12(OT16/DATA)
13
S13(OT17/SFSY)
14
S14(OT18/LRCK)
15
P8-0(S15/BCK)
16
P8-1(S16/AOUT)
17
P8-2(S17/MBOV)
18
P8-3(S18/IPF)
36
35
34
33
P2-3(DATAin)
90
RST
19,96
46,75
47,76
MV
DD
20,95
MV
SS
P2-2(LRCKin)
P2-1(HSO in)
P2-0(EMPHin)
89
37
IN2
IN1(BCKin)
38
TESTC
88
TESTM
91
HOLD
39
OT19(HSO)
40
OT20(SPCK)
41
OT21(SPDA)
42
OT22(COFS)
43
DOUT
44
SBSY
45
SBOK
50
LPFN
51
LPFO
53
PV
REF
54
VCOF
48
P2V
REF
49
PDO
50
TMAX
56
SLCO
57
RFI
AVSS
AVDD
RFCI
RFZI
RFRP
FEI
SBAD
TEI
TEZI
FOO
TRO
V
REF
69
RFGC
70
TEBC
71
FMO
72
DMO
73
2VREF
74
SEL
ZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF
Reset
F/F
OT19-22
Correction circuit
16k SRAM
Address
Stack Reg.
(8Level)
AD
Conv.
Port 3
BUZR
Port 4
Serial
Interface
Interrupt
Cont.
Timer
Port 1
X’tal
OSC
MPX
CPU clock
SBSY
ROM
(16 x 8192 Step)
Data Reg(16 bit)
Program
Counter
Instruction
Decoder
RAM
(4 x 512 word)
G-Reg.
SBSY
CLCK, DATA, SFSY,
LRCK, BCK, MBOV, IPF
Reset
CD Reset
Audio out Digital out
AD
ZDET
PWM
PX’tal OSC
Clock
gene.
1 bit DAC
RAM
LPF
ROM
V
REF
CLV
servo
Synchronous
guarantee EFM
decode
VCO
Sub code decoder
SERVO
control
Digital equalizer
Automatic adjustment
circuit
CD clock V
REF
DA
Data
slicer
PLL
TMAX
V
REF
P2-0~P2-3
IN1
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