Sharp Compet 17

KCLR, KCE,
KAS, KS, KMD, KD,
KRC, KDP,
KMC, KMR,
KMAS, KMS
V
–24
M Register
(user memory, 48 bits)
W Register
(2nd operand, 48 bits)
X Register
(displayed operand, 48 bits)
12 Nixie Displays
Sharp Compet 17 Calculator
Section: Block Diagram
Page: 3 Rendition: 2020 May 20
PY
Ring Counter
PW
Ring Counter
PXI
Ø1
Ø2
ØB n
bit timing
ØD n
digit timing
Display Latch
(4 bits)
V
CL
Keyboard
Control
CARRY
Arithmetic
(BCD
serial adder, 4
bits)
C
Flag
D
Flag
M
Flag
S
Flag
F
Flag
J
Flag
G
Flag
State
Sequencing
S1
S6
CX…
CA…
CB…
X Outputs
1-of-10
Decoder
and Drivers
Timing
Numeral
Encoder
K0…K9
KNUM
M
W
X
KNDP
Decimal
Point
Driver
logic supplies
display supplies
V
+90D
V
+90
V
+190
Power Supply
000987654321.
Decimal Point (PX)
Ring Counter
Ø3
XC1
XC2
XC4
XC8
W
X
CSUB
CTC
Arithmetic
Outputs
CSUM
CWW
CWX
CWØ
KMC
CMX
CMØ
M Outputs
W Outputs
P Cycle
Generator
P
PX
CPYPX
CPW…
CPX…
PW
PY
PY Outputs
PW
Outputs
PX Outputs
IDLE