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Copyright 2005© Siemens AG
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Service Repair Documentation
Level 2.5e – C75
Release 1.0
S
upported Standards
• GSM speech FR, HR, EFR and AMR-NB
• GSM data 2.4kbit/s, 4.8kbit/s, 9.6kbits, and 14.4kbit/s
• HSCSD class 10
• GPRS class 12
Processing cores
• ARM926EJ-S 32-bit processor core with operating frequency up to 125 MHz for
controller functions
• TEAKLite DSP core with operating frequency 104 MHz.
ARM-Memory
• 8 kByte Boot ROM on the AHB
• 96 kByte SRAM on the AHB, flexibly usable as program or data RAM
• 8 kByte Cache for Program (internal)
• 8 kByte tightly coupled memory for Program (internal)
• 8 kByte Cache for Data (internal)
• 8 kByte tightly coupled memory for Data (internal)
TEAKLite-Memory
• 80 kwords Program ROM
• 4 kwords Program RAM
• 48 kwords Data ROM
• 27 kwords Data RAM
Shared Memory Blocks
• 1.5 kwords Shared RAM (dual ported) between controller system and TEAKLite.
Functional Hardware blocks
• CPU and DSP Timers
• Programmable PLL with additional phase shifters for system clock generation
• GSM Timer Module that off-loads the CPU from radio channel timing
• GMSK Modulator according to GSM-standard 05.04 (5/2000)
• Hardware accelerators for equalizer and channel decoding
• Advanced static and dynamic power management features including TDMA-Frame
synchronous low-power mode and enhanced CPU modes (idle and sleep modes)
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