mechanism allowing the CPU to read the extension ROM in the interface
for microdrive and RS232 applications.
4.5.3
Links
H and N,
shown
directly
above
IC5,
allow
a
second
source
ROM to
be
fitted.
The
Hitachi
(H) and NEC (N)
ROMs
use
different pins
for
the
enable
and
select
inputs (i.e. pins
20 and
27).
The
links
allow
the inputs to be reversed accordingly.
4.5.4 Standard 16k RAM (IC6-IC13). The eight 16k RAM ICs making up the
standard 16k x 8 bit RAM memory are organised as a matrix of 128 rows
x 128 columns. Thus, separate 7-bit row and column addresses are
reguired to access any one of the locations. These addresses are
supplied by the CPU on address bus A13-AO via an address multiplexer
IC3/IC4.
The low
order address
bits
A6-AO
give
the row
address
and
are
selected
at the
beginning
of the
memory
access cycle
when
initially
the RAS
output
from
the ULA is
high. Later,
as the row
address
is
latched,
RAS
goes
low
selecting
the
high order address
bits
A13-A7 giving the column address.
4.5.5 The RAS/CAS outputs from the ULA are generated in seguence in response
to
MREQ
and A14
from_the
CPU.
The
DRAMWE
output, also
from
the ULA is
a
decode
of the
RD/WR
waveforms
telling
the RAM to
expect
either
a
read or a write cycle.
4.5.6
It is
also apparent
from
the
circuit
diagram
that
the ULA can
access
RAM by generating a set of addresses independent of those generated by
the CPU. The address port for the RAM is therefore dualled by the
insertion
of
small value
resistors
(R17-R23)
on the
address
multiplexer side of the RAM. This ensures that where there is likely
to be conflict between the ULA and CPU, the ULA address has priority.
Priority
is
assigned
on the
basis
that
the ULA
must
access
the
memory
mapped display area in the RAM at set intervals in order to build up
the video for the TV display. If the ULA is about to access the RAM
and it detects either A14 or A15 (i.e. the CPU is also about to access
the RAM) the ULA inhibits the CPU clock temporarily halting the CPU
memory
transaction
until
its own
transaction
is
completed.
4.5.7 Resistors
Rl to R8, in
series
with
the
data
bus
lines,
perform
a
similar
function
to the
address portplr£sistors described above.
They
ensure that the ULA does not 'see' CPU write data while the ULA is
accessing the RAM.
4.5.8 Refresh for the standard 16k dynamic RAM is accomplished during normal
read cycles, i.e. most rows are refreshed each time the ULA accesses
the
memory
mapped
display area during
picture
compilation;
the
remaining
rows
are
refreshed
as a
result
of
other read
cycles
also
known
to
occur
at
regular
intervals
within
the
refresh period.
1.5
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