4.5.9
32k
Expansion
RAM
(IC15-IC32).
The
eight
32k ICs
making
up the 32k x
8 bit expansion RAM are in fact 64k ICs with either row or column
drop-out rendering one half of the memory non-functional. In order to
accommodate
the
Texas
Instruments
RAM
(Type
TMS
4532)
or the
optional
OKI RAM
(Type
MSM3732)
a set of
links
are
provided,
visible
on the
circuit
diagram
above
the
address
multiplexer
IC25/IC26.
These
links
not only cater for the different manufacturer (Issue 3 Spectrums only)
but also allow, in both instances, one of two 1C versions to be
selected depending on which half of the RAM (top, bottom, left or
right) is functional. The links are respectively TI and OKI
(manufacturer - Issue 3 Spectrums only), -3/-4 (TI version) and -H/-L
(OKI version - Issue 3 Spectrums only).
NOTE:
It is
essential
when
replacing
ICs in
this
area
that
all
RAMs
carry
the
same
manufacturers
part
number
and
that
the
links
are selected accordingly.
4.5.10 The expansion RAM is organised as a matrix of 128 rows x 256 columns
(TI
RAMs)
or 256
rows
x 128
(OKI
RAMs).
Thus,
separate
7/8 bit row
and column addresses are required to access any one of these
locations. These addresses are supplied by the CPU on address bus
A14-AO via an address multiplexer IC25/IC26. For example, when
accessing the TI RAM the low order address bits A6 to AO give the row
address; AR is held low on the -3 version selecting the top half of
the
memory
and
high
on the -4
version
selecting
the
bottom
half.
The
column
address
is
given
by the
high order address
bits
A14-A7.
4.5.11
Row/column
address
selection
and
RAS/CAS
timing
for the
RAM
is
decoded
in
IC23/IC24
from
inputs
supplied
by the
CPU, i.e. address
line
A15
selecting
addresses
8000
upwards,
and
MREQ
heralding
a
memory
read
or
write cycle.
A
theoretical
timing diagram
illustrating
the
RAS/CAS
waveforms is given in Figure 1.2.
5. INPUT/OUTPUT
5.1 The input/output section of the Spectrum is centered round the ULA
(IC1). The functions performed within the device include TV video
compilation, keyboard scanning and tape input/output. It also derives
and
controls
the CPU
clock
(<j>CPU)
using
an
external
14 MHz
crystal
XI,
and
drives
the
loudspeaker
when
a
'BEEP'
instruction
is
being
executed.
Each
of
these
sections
and the
supporting
circuits
are
described below.
5.2 TV Picture Generation
5.2.1 The video compilation section of the ULA operates in conjunction with
the
memory
mapped
picture
display area
in the
standard
16k
RAM,
the
colour (chrominance) modulator (IC14) and the UHF modulator. This
combination produces a high resolution, 24 line x 32 character, eight
colour TV display.
1.6
To Next Page
