Sony CDP-295 - Technical Diagrams and Component Data; IC Pin Functions and Block Diagrams

GDP-î9s
12951491
4-1- PrN
FUNCïON
OF
tC101 AND
te!01
sEcïoN 4
DIAGRAMS
.
tct01
137
PIN
FUNCTION
Pin
No.
Pin Name
1lO
Description
I vc
GND when
two
(+1
dual
power
supplies
ane
in use,
or the
ce'ter vorta6e
(2.5v)
when
a
single power
supply
is in use,
t
FGD
I Time
constants
for
gain
switching
in
normal
mode/down
mocle
and
conncted
between
the
FGD
and
FSJ
pins.
for focus
gain
are
3
FS3
I
4
D
FLB
FEO
I
o
The
capacitor
for low
frequency
boost
in the
focus
servo
loop
is connected,
Focus
drive
output.
6
7
FE_
SRCH
I
I
Inverted
input
to
focus
amplifier.
Time
constmts
to
tenerate
the
focua
search waveform
are
connected.
8
TGU
Time
constants
for
gain
switching
in
normar
mo<re/up
-od.
on,r
fo,
ilJtgllIll
connected
between
TGU
pin
and
TG2 pin.
I
TG2
I
l0
AVCC
'^"e'v6
pvwçr
èu,,pry
rov
wnen
=
.'uar power
supplies
are
in
use,
5v
when
a
single
power
supply
is
in
use.)
Tracking
drive
output.
Inverted
input
to
tracking
amplifier.
Non-inverted
input
to
sled
amplifier.
Sled
drive
output.
Non-inverted
input
to
sled
amplifier.
l1
t2
13
l4
l5
TAO
TA_
sL+
sLo
sL-
o
I
I
o
I
t6
t7
l8
l9
20
ESET
ISET
SSTOP
AVEE
DIRC
I
I
I
I
rne
oluKJ,
pnase
compensator
resistor
is connected
to this pin,
The
current
setting
resistor
is connected
to
this pin.
The
limit
switch
ie
connected
to this
pin.
Analog
power
supply (-EV.when *
dual power.rppli",
are
in
use,
or
GND
when
a
single
power
supply
is in
use.)
Direct
control
pin.
21
22
23
24
25
LOCK
CLK
XLT
DATA
XRST
I
I
I
I
I
vrçl,
ru'-awëJ
preventton
clrcutt
operates
when
this
signal
is
"L".
Serial
data
transfer
clock
input
that
ie
supplied
from
CpU
(or
DSp).
Latch
input
from
CpU
(or
DSp).
Serid
data
input
from
CpU
(or
DSp).
System
reset.
"L"
to
reset.
-
Ôrrtnrr+^.---l-:-- -
26
27
28
29
30
C.OUT
SENS
DGND
MIRR
DFCT
o
o
o
o
SENS
output.
3"i,1*:::1rti3l;t"ïi
when
t
<ruar
power
supplies
are
in
use.
GND
when
Mirror
output.
)efect
output.
"H"
when
defective,
rqùw-éssymmerrv
"o.tF
31
32
33
34
35
ASY
EFM
FOK
ac2
ccl
I
o
o
I
o
IFM
comparator
output,
rocus
OK.
)efect-bottom-hold
input
(inout
by
capacitive
coupling).
)efect-bottom-hold
nrrr^,,+
36
37
38
39
40
DVCC
CB
CP
RFI
RFO
t
I
I
I
Digital
power
""""1".
J]?î
power
supply
is
in
use.)
The
defect-bottom-hold
capacitor
is
connrcted
to
this
pin.
The
mirror
hold
capacitor
is
connected
to
this
pin.
RF
signal
input
(input
by
capacitive
coupling).
Pewer
supPttes
in
use.
*5v
when
a
single
4l
42
43
44
45
DVEE
TZC
TE
TDFCT
ATSC
I
I
I
I
pprres
are
in
use.
GND
when
a
single
power
supply
is
in
use.)
Tracking
zero-cross
comparator
input.
Tracking
error
input.
The
defect
prevention
hold
capacitor
is
connected
to
this
pin.
Anti-shock
inout.
46
47
48
FZC
FE
FDFCT
I
I
I
Focus
error
input.
The
defect
prevention
hold
capactior
is
connected
to
this
pin.
-8-