Tait TM8105 Service Manual

90 Circuit Descriptions TM8100/TM8200 Service Manual
© Tait Electronics Limited June 2006
Figure 3.12 Block diagram of the digital board (TM8200 radios)
+1V8+3V3
Trans-
mitter
DIG TX INH
DIG SYN EN
SYN LOCK
DIG SYN TR SW
DIG SYN FAST
DIG SYN LATCH
SYN DIG FREF
Frequency
Synthesizer
DIG SYN SPI DO
DIG SYN SPI CLK
DIG RX LE
RX DIG LD
DIG RX NB EN
Receiver
DIG RX EN
CDC2 DIG SDTO
DIG CDC2 SDTI
DIG CDC2 CLK
DIG CDC2 LRCK
DIG DAC SPI DO
DIG DAC SPI CLK
DIG DAC LATCH
DIG CDC ARSM
CDC DIG VSFS
CDC DIG VSDO
DIG CDC VSDI
CDC DIG BSOFS
CDC DIG BSDO
DIG CDC ASFS
DIG CDC ASDI
CDC DIG ASDO
DIG AUD PA EN1
DIG AUD PA EN2
+1V8
CODEC
and
Audio
Serial
Flash
DGND
AGND
DIG CH SPI CLK
DIG CH SPI DO
ITF CH SPI DI
DIG CH LE
ITF CH GPI1
DIG CH GPO1
ITF CH PTT
ITF CH HOOK
ITF ON OFF
ITF IOP GPIO1-7
DIG IOP TXD
ITF IOP RXD
ITF AUX GPI1-7
DIG AUX GPO4-7
DIG AUX TXD
ITF AUX RXD
DIG CH TXD
ITF CH RXD
DIG PSU LATCH
DIG WD KICK
DIG TX EN
+3V3
PSU SYS RST
DIG RX EN
Interface
Power
Supply
FPGA
DSP
McBSP0
McBSP1
1V8
Regulator
+1V8
AGND
+3V3
Factory Connector
DSP JTAG Signals:
FPGA JTAG Signals:
JTAG TCKFPGA
JTAG TMSFPGA
FPGA JTAG TDO
JTAG FPGA TDI
JTAG TCKDSP
JTAG TMSDSP
DSP JTAG TDO
JTAG DSP TDI
JTAG TRSTDSP
DSP JTAG EMU0
DSP JTAG EMU1
DSP JTAG (x7)
FPGA JTAG (x4)
Digital Board
DIG SLP EN
+1V8+3V3
1V5
Regulator
+1V5
+1V5
SRAM
CONTROL
ADDRESS
DATA
Flash
Memory
IO
RESET
4
4
PSU SYS RST
BIRDIE
FPGA CLOCK
System
Clock
DIG SYS CLK
Signal Types:
RF
analog
clock
digital
asynchronous serial data
synchronous serial data
DIG CDC RST

Tait TM8105 Specifications

General

Brand	Tait
Model	TM8105
Category	Radio
Language	English