Teac MT-20D-IO - Page 36

3-4-4 Host interface control
The hardware of the host interface control consists of one gate array logic
IC (U11/2310 IC, interface control) and driver/receiver.
For the details of the interface signal timing, refer to the "MT-2ST/20D
Specifications".
Description is given below on the major operations of this IC.
HBO to HB7, and HBP are a bidirectional bus.
To prevent the bus competition between the driver IC and HOST side driver,
there is the timing relation as shown in Fig. 314 among this bus, DIR and
HBOEN.
DIR(HI
~
H80EN(HI
I I~_
H8~ '" H87,H8P
I I ~,--------) i I
W lJJ
CD ® ®
®
®
TI ~ 1390s
Tz > 1380s
T3 > 1380s
T4 ~ 1390s
(Note) DIR(H) Indicates the transfer from MTU to HOST,
when signal level goes high.
HBOEN(H): Indicates that the driver of MTC is validated
when the signal level goes high, and the
receiver is validated when the signal level
goes low.
Fig. 314 Interface bus timing
- 324 -