Teac MT-20D-IO - Page 53

CD REQ is set to FALSE 0.5 to 1.5 clock after ACK is outputted. At
this timing. the contents on the data bus (HBO - HB7, HBP) are
latched in the internal data register of 2557.
~ Data (command) is written from 2557 to RAM by IOR(L) and MW(L).
Q) EOP(L) is outputted from DMAC together with HDACK(L) of the end
byte (6th byte) of command, and thereby the interrupt request HINT
to CPU is outputted.
Remark
The
signal ® is a gate signal to prevent the follow-
ing REQ or HINT from being outputted earlier, when the
ACK response is late. U21 and U22 are logic circuits
for such purpose.
(3) Write data transfer
This transfer timing is exactly the same as in the command transfer.
For the write data transfer, DMAC is operated in 512 bytes units.
The beginning REQ of each data block is outputted by an instruction
from CPU.
(4) Read data transfer
This timing is nearly the same as in the write data transfer. The
beginning HDRQ of each data block is set by an instruction from CPU.
The beginning REQ is outputted by DACK(L) with respect to the above.
Fig. 324 shows the read data transfer timing.
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