Teac MT-20D-IO - Page 59

CPU
BUS
----
..----
WRITE
GCR
SHIFT
DATA
MPX
r---
CONVER-
r--
REG.
REG.
TER
r
L....;..
CRC
GENERATOR
READ
GCR
SHIFT
DATA
CONVER-
t--
REG.
REG.
TER
I CRC CHECKER ~
READ
CLOCK
VFO
Fig. 326 Write/read control logic block diagram
- 347 -
r--
CMT SIDE
WD
(WRITE DATA)
RD
(READ DATAl