Theory of
Operation-2225
Service
CHANNEL
2
DISPLAY ONLY. The CH 2 position of
S550 holds the RESET input of
U540A LO through
CR538, and the SET input is held HI by pull-up
resistor
R538. This resets U540A, making the Q out-
put of
U540A LO and the
b
output HI. The Channel 2
Preamplifier signal is then enabled to drive the Delay
Line Driver, while the CH 1 Preamplifier is disabled.
To display the ADD, ALT, or CHOP formats, S550
must be in the BOTH position to ground the A, C,
and
F
pins of S545.
ADD DISPLAY. In the ADD position of S545, both the
SET and RESET inputs of
U540A are held LO by
CR534 and CR537. This forces the Q and
b
outputs
of
U540A both HI, and signal currents from the
Channel 1 and Channel 2 Preamplifiers add together
to drive the Delay Line Driver.
CHOP DISPLAY. In the CHOP position, the
CHOP ENABLE line is held LO, keeping the Q output
of flip-flop
U540B HI. This enables CHOP multi-
vibrator U537D to begin switching. The switching
rate is determined primarily by the component
values of
R544, R545, and C545. The output of
U537C (the inverted output of the multivibrator
circuit) supplies the CHOP clock to flip-flop
U540A
via U537A. The output of U537C also drives U537B,
the CHOP Blanking Pulse Generator.
Coupling capacitor C547 and resistors R547 and
R548 form a differentiating circuit that produces
positive-going and negative-going short duration
pulses. These pulses are inverted by
U537B to gen-
erate the Chop Blank signal to the Z-Axis Amplifier.
The pulses blank the crt during CHOP switching
times.
The Alt Sync signal applied to one input of
U537A is
HI except during
Holdoff. This allows the output of
U537C to be inverted by U537A which drives the
clock input of
U540A. Since the
b
output of U540A
is connected back to the D input, and both the SET
and RESET inputs are HI (unasserted), the outputs
of
U540A toggle (change states) with each clock
input. The Delay Line Driver is then driven alternately
from the Channel 1 and Channel 2 Preamplifiers at
the CHOP rate.
ALTERNATE DISPLAY. In ALT, the CHOP ENABLE
line is held HI, disabling CHOP multivibrator
U537D.
The output of U537C will be HI and the CHOP BLANK
signal from
U537B will be LO. Input signals to U537A
are the HI from U537C and the ALT SYNC signal from
the
Holdoff circuitry in the Sweep Generator. The
output of
U537A will then be the inverted ALT SYNC
signal that clocks Channel Select flip-flop
U540A.
This causes the outputs of U540A to toggle at the
end of each sweep so that the Channel 1 and
Channel 2 Preamplifiers alternately drive the Delay
Line Driver.
Delay Line Driver
The Delay Line Driver converts the signal current
from the Vertical Preamplifiers into a signal voltage
for input into the Delay Line. Transistors
Q202,
Q203, Q206, and Q207 form a differential shunt
feedback amplifier with the gain controlled by R216
and
R217. Common-mode dc stabilization of the
Delay Line Drive Amplifier is provided by
U225.
Should the voltage at the junction of R222 and R223
deviate from zero, U225 will sink or source base
current to Q202 and Q203 through R202 and
R203.
This will return the outputs of the Delay Line Driver to
an average dc value of zero volts. Delay Line DL224
provides a vertical signal delay of approximately 90
ns so that the Sweep Generator has sufficient time
to produce a sweep before the vertical signal that
triggered the sweep reaches the vertical deflection
plates.
Vertical Output Amplifier
The Vertical Output Amplifier drives the vertical
deflection plates of the crt. Signals from the Delay
Line go to a differential amplifier formed by Q230
and Q231 with low- and high-frequency compensa-
tion provided by the RC networks between the emit-
ters. Thermal compensation is provided by thermis-
tor
RT236, and overall circuit gain is set by R233.
The output stage of the amplifier is two, compound-
shunt transistor pairs, Q254-Q256 and Q255-Q257,
that convert the collector currents of Q230 and Q231
to proportional output voltages. Resistors R256 and
R257 serve as feedback elements. High-frequency
compensation is provided by C256 and
C257.
Scam
by
ARTEK MEDL4
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