3-18 TM109902 (5/03)
USE OR DISCLOSURE OF DATA CONTAINED ON THIS PAGE IS SUBJECT TO THE
RESTRICTION ON THE TITLE PAGE OF THIS DOCUMENT.
C OMMAND S YSTEMS D IVISION
A7
A6
A5
A4
A3
A2
A1
A0
Q1
Q2
Q3
GND
VCC
A8
A9
A11
C/VPP
A10
E
Q8
Q7
Q6
Q5
Q4
1
2
3
4
5
6
7
8
9
10
11
12
IC62
VCC
QE
QE
CE LOGIC
QE AND
V
DECODER
OUTPUT BUFFERS
DATA OUTPUTS
00-07
Y GATING
32.768 BIT
CELL MATRIX
32.768 BIT
CELL MATRIX
CE
VPP
GND
PIN NOMENCLATURE
AQ-A11
E
C/VPP
Q1-Q8
VCC
13
14
15
16
17
18
19
20
21
22
23
24
DDRESS
CHIP ENABLE
OUTPUT/ENABLE/+21V
OUTPUTS
+15V POWER SUPPLY
X
DECODER
30761
AC-ALL
ADDRESS
INPUT
TYPE: 2732
DESCRIPTION: 32K (4KXB) UY ERASABLE FROM
PIN LOCATION DRAWING: G
MOS DEVICE: USE SPECIAL HANDLING PROCEDURE
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•
•
•
•
•
•
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Figure 3-3. Integrated Circuit Logic Diagrams (Sheet 3 of 15)
The document reference is online, please check the correspondence between the online documentation and the printed version.
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