Texas Instruments 99/4A - Page 24

HOLDA (HOLD ACKNOWLEDGE) When active (high), HOLDA indicates that the
processor is in the hold state and that the outputs (MEMEN, WE and
DBIN) are in the high inpedance state thus making it possible for an
external device to use the buses and access memory.
The timing diagram -For direct memory access is given i f Figure
9 p „29.
IN AND OUTPUT (I/O)
The TMS 9900 has two possibilities -For communicating with external
devices:
A. Addressing the device as memory.
B. Using the communication resister unit (CRU).
The CRU makes it possible to communicate with external devices with
•fewer lines. Only A3 through A14, CRUIN, CRUOUT and CRUCLK are used.
The CRU I/O bus makes it also possible to address bits or words
OUTPUT
Output with the CRU interface is performed as follows:The processor
addresses the bit to be set. This address is decoded and enables a
latch to the data present on the CRUOUT lines on CRUCLK.
INPUT
Input is performed only with the address bus and CRUIN. Again the
processor addresses the bit to be read. The system . hardware decodes
the bit address on A3 through A14 and enables the addressed bit to
put its value on the CRUIN line. The bit is then fetched by the
TMS 9900.
TIMING DIAGRAM
A timing diagram of CRU operations is given in figure 10,p30.
The TI 99/4 home computer uses both ways of I/O to communicate with
internal and external devices.
INTERRUPT HANDLING
Interrupt processing logic on the TMS 9900 uses the following inputs.
INTREQ INTERRUPT REQUEST. When active (low) INTREQ indicates that
an external interrupt is requested. If INTREQ is active,
the processor loads the data on the interrupt-code input
lines ICO through IC3 into the internal interrupt-code
storge resister. This code is compared to the interrupt
mask bits of the enabled interrupt level, the TMS 9900
interrupt sequences is initiated. If the comparison fails,
the processor ignores the request. INTREQ should remain
active and the processor will continue to sample ICO
through IC3 until the program enables a sufficiently low
priority to accept the requested interrupt.
ICO INTERRUPT CODES. ICO is the most sighificant bit of the
IC1 interrupt code, which is sampled when INTREQ is active.
ICC When ICO through IC3 are LLLH, the highest external
IC3 priority interrupt and when HHHH the lowest prority is
being requested.
In this system, ICO,IC's and ICC are tied to VSS,and IC3 is tied to
9CC, thus if INTREQ is active, it is always considered the highest
pri ori ty .
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