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Texas Instruments 99/4A - Page 23

Texas Instruments 99/4A
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CENTRAL
PROCESSING
UNIT
GENERAL
DESCRIPTION
THE
99/4A
Home
Computer
use
the
Texas
Instruments
TMS
9900
mi
preprocessor
.
It
provides
the
system
with
a
15
bit
address
and
18
bit
data
bus
for
communication
with
external
memory.
It
also
has
input
and
output
pins
for
serial
in
and
output,
interrupt
handling
and
memory
control
(see
-Figures
3
and
4,
p.
20-23).
MEMORY
INTERFACING
The
TMS
9900
inter-Faces
with
memory
by
means
of
a
16
bit
data
bus
(D0-D15)
,
the
15
bit
address
bus
(A0-A14)
and
the
-Following
control
signals.
MEMEN
MEMORY
ENABLE.
When
active
(low),
MEMEN
indicates
that
the
address
bus
contains
a
memory
address
WE
WRITE
ENABLE,
write
data
is
memory
.
When
active
(low)
WE
indicates
that
memor
available
from
the
TMS
9900
to
be
written
into
DBIN
DATA
BUS
IN.
When
active
(high),
READY
indicates
that
memory
will
be
ready
to.
read
or
write
d^uring
the
next
clock
cycle.
When
not
ready
is
indicated
during
a
memory
operation,
the
TMS
9900
suspends
further
operation
(e.g.
enters
a
wait
state)
until
READY
becomes
active
again,
after
which
the
memory
read/write
cycle
is
completed.
This
signal
enables
the
use
of
slow
memory
devices
with
the
TMS
9900.
WAIT
WAIT.
When
active
(high),
WAIT
indicates
that
the
TMS
9900
has
entered
from
memory.
a
wait
state
because
of
a
not-ready
condition
Timing
diagrams
for
read
and
write
cycles,
with
and
without
wait
states,
are
given
in
Figures
5-8,
p.
25-28.
DIRECT
MEMORY
ACCESS
Performing
memory
access
without
interference
of
the
TMS
9900
is
called
direct
memory
access
(DMA).
For
this
purpose
the
following
control
lines
are
available.
HOLD
When
active
(low),
HOLD
indicates
to
the
processor
that
an
external
controller
desires
to
use
address,
data
and
memory
control
signals.
The
TMS
9900
enters
the
hold
state
following
a
hold
signal
when
it
has
completed
its.present
memory
cycle.
The
processor
then
places
the
address
and
data
buses
in
the
high-impedance
state
along
with
MEMEN,
WE
and
DBIN
and
responds
with
a
hol'd
ackowledge
signal
(HOLDA)
.
When
HOLD
is
removed,
the
processor
returns
to
normal
operat
ion
.
15

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