Texas Instruments 99/4A - Page 26

GROUND Pin connections 26 and 40 are for ground.
CLOCK INPUTS
Clock inputs 01, 02, 03 and 04 are input on pins 8, 9, 25 and 23
respecti vely .
ADPRESS bus
The 99/4 uses the address bus internally without further
buffering, except for 014, which is used on the GROMs (see 1/0 bu
descri pti on ) .
DATA BUS
Internal RON and RAN uses the data bus without buffering. To
connect the data bus to internal 8 bit devices and for in and
output, a special 16 to 8 bit interfacing circuit is used.
CRU BUS
CRUOUT, CRUI and CRUCLK are used internally without buffering.
INTERRUPT HANDLING
Interrupt vector pins 33 through 36 are preset to code LLLH, the
highest external priority interrupt. So the 99/4 knows only ce
interrupt level. The INTREO line is connected to the TNS 9901,
which handles the interrupts.
RESET
The system resets during power up or when a solid state software
command module is inserted. This is done by connecting RESET pin
6 to pin 4 of the system clock generator (U601).
LOAD
The load function or pin 4 is connected to the 1/0 Port via
resistor R523.
WRITE ENABLE
The WE function or pin 61 is used by fast system RAN without
buffering and is modified by timing and control for other
devices.
IAQ/HOLDA
The instruction aguisition signal on pin 7 and the hold
acknowledge signal on pin 5 are combined on OR-gate U6C'5 to
generate a combined signal.
NENORY ENABLE (NENEN)
This signal is buffered by OR gate U605 for further use in and
outside the 99/4. R607 is used as a pull up resistor to +5 volt
to assure that memory is disabled during power up.
DBIN
The DBIN signal on pin 29 is buffered twice by inverting gates
U602 for use within the 99/4 system.
READY/HOLD
READY and HOLD on pins 62 and 64 are combined to form one signal.
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