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Texas Instruments 99/4A - Page 27

Texas Instruments 99/4A
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A
study
of
9900
's
internal
structure
is
useful
when
trying
to
understand
the
operation
of
the
IC.
The
architecture
of
the
9900
microprocessor
is
shown
in
the
diagram
of
figure
3,p.2O.
This
shows
the
internal
features
within
the
CPU.
These
features
include:
*
The
ALU
t
3
Multiplexer
buses
t
Control
Logic
and
Control
RCM
*
Internal
Registers:
Memory
address
register,
shift
register,
status
register,
source
data
register,
shift
counter,
workspace
register,
instruction
register,
and
auxiliary
register
TI
and
T2.
The
ALU
(Arithmetic
Logic
Unit)
is
a
16-bit,
parallel
logic
network
used
in
the
execution
of
the
9900'
s
instructions
.
The
unit
performs
arithmetic
functions,
log,
and
comparisons.
The
multiplexer
buses
are
used
in
the
transfer
of
flow
and
data
in
the
CPU.
The
control
circuitry
provides
the
signals
necessary
for
correct
gating.
The
control
logic
and
control
ROM
provide
the
necessary
signals
for
the
correct
sequencing
of
operation
of
the
CPU's
instructions
.
This
is
accomplished
with
the
aid
of
the
input
control
signals
and
master
timing.
Among
the
internal
registers
there
are
three
which
are
key
architectural
features
of
the
CPU.
These
registers
are
the
workspace
pointer
that
contains
the
location
of
the
first
word
in
the
workspace.
The
program
counter
contains
the
address
for
the
next
word
which
is
to
be
used
in
the
execution
of
an
instruction.
The
status
register
determines
if
the
conditions
necessary
for
an
instruction
execution
have
been
met.
This
is
done
by
the
setting
of
f
1
ags.
In
the
operation
of
the
9900,
sixty-nine
instruction
words
can
be
used.
A
list
of
the
9900's
instruction
set
can
be
found
in
Table
3,p.31.
These
instructions
are
used
to
perform
arithmetic
operations,
logic,
comparisons,
and
manipulation
operations
on
data.
They
are
also
used
for
the
loading
and
storing
of
data
within
the
CPU's
internal
registers.
Data
transfer
between
the
external
memory
system
and
external
devices
is
also
made
possible
with
the
instructions
via
the
CRU.
Instructions
are
also
used
as
control
functions
within
the
CPU.
The
external
memory
used
with
the
TMS
9900
in
the
TI
99/4
and
TI
99/4A
consists
of
two
TMS
4732'
s
and
two
MCM
6810P's.
The
TMS
4732'
s
are
4K
X
8bit
ROMS
and
are
addressed
via
lines
A3-A14
of
the
address
bus.
However,
one
of
the
4732'
s
uses
the
D1-D7
lines
on
the
data
bus
while
the
other
uses
data
lines
D8-D15,
thus
combining
the
two
6810'
s
are
combined
to
form
a
128
X16
bit
RAM.
One
slight
difference
from
the
4732's
is
that
the
6810's
are
addressed
by
address
lines
A8-A14.
The
9900
uses
three
control
signals
during
operation
of
the
external
memory
read
and
write
to
control
the
use
of
the
address
and
data
busses.
These
signals
are
DBIN,
—
MEMEN,
and
-WE.
During
memory
read,
DBIN
and
-MEMEN
are
active,
while
-WE
is
not.
The
active
signals
allow
an
output
onto
the
address
bus
indicating
the
desired
memory
location
to
be
read.
DBIN
is
active
(high)
when
the
9900
has
disabled
its
output
buffers
and
is
used
in
the
system
to
enable
data
input
to
the
processor.
19

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