Texas Instruments 99/4A - Page 30

TMS 9900
ARCHITECTURE
Product Data Book
TABLE 2 (CONTINUED!
SIGNATURE
P1N
I/O
DBIN
29
OUT
MEMEN
63
OUT
WE 61
OUT
CRUCLK 60
OUT
CRUIN
31
IN
CRUOUT
30
OUT
INTREQ 32
I
IN
ICO (MSB)
36
IN
IC1
35
IN
IC2
34
IN
ICO (LSB)
33
IN
hold
64 IN
HOLOA
5
OUT
READY
62
IN
WAIT 3
I
OUT
DESCRIPTION
BUS CONTROL
Data bus in. When active (high). DBIN indicates that the TMS 9900 h as disabled its output buffers to
allow the memory to piece memory-read data on the data bus during MEMEN. DBIN remains low in
all other cases except when HOLOA it active.
Memory enable. When active (low), MEMEN indicates that the address bus contains a memory address.
Wore enable. When acnw (low), WE indicates that memory-write data is available from rhe TMS 9900
to be written into memory.
CRUdocL When active (high), CRUCLK indicates that external interface logic should sample the
output data on CRUOUT or should decode external instructions on A0 through AX
CRU data in, CRUIN. normally driven by 3 -state or open-co I lector devices. receives input data from
external interface logic. When the processor executes a STCR or TB instruction,it samples CRUIN for
the level of the CRU input bit specified by the address bus (A3 through A14),
CRU data out. Serial I/O data appears on the CRUOUT line when an LDCR. S8Z. or S0O instruction
is executed. The data on CRUOUT should be sampled by external I/O interface logic when CRUCLK
goes active (high).
I NTERRU PT CONTROL
Interrupt request. When active (low), INTREQ indicates that an external interrupt is requested. If
INTREQ is active, the processor loads the data on the interrupt-code-input lines ICO through IC3 into
the internal interrupt-code-storage register. The code is compared to the interrupt mask bits of the
status register. If equal or higher priority than the enabled interrupt level (interrupt code equal or less
than status register bits 12 through 15) the TMS 9900 interrupt sequence is initiated. If the
comparison fails, the processor ignores the request. INTREQ should remain active and the processor
will continue to sample ICO through IC3 until the program enables a sufficiently low priority to accept
the request interrupt.
Interrupt codes. ICO is the MSB of the interrupt code, nhtch is sampled when INTREQ is active. When
ICO through ICO are LLLM. the highest external-priority interrupt is being requested and when HHHH,
the lowest-prioritv interrupt is being requested.
MEMORY CONTROL
Hold. When active (low), HOLD indicates to the processor that an external controller (e-g.. DMA
device) desires to utilize the address and data buses to transfer data to or from memory . The
TMS 9900 enters the hold state following a hold signal when it has completed its present memory
cydt ’ The processor then places the address and data buses m the high impedance state (along with
WE. MEMEN. and DBIN) and responds with a hofd-ecknowiedge signal (HQLDA). When HOLD is
removed, the processor returns to normal operation.
Hold acknowledge. When active (high). HOLOA indicates that the' processor is in the hold state and
the address and data buses and memory control outputs (WE. MEMEN, and D81N) are <n the
high-impedance state.
Ready. When active (high). READY indicates that memory will be ready to read or write during the
next clock cycle . When net-ready ts indicated during a memory operation, the TMS 9900 enters a wait
state and suspends internal operation until the memory systems indicate ready.
Wait. When active (high), WAIT indicates that the TMS 9900 has entered a wait state because of a
net-ready condition from memory.
•If the cycle follow.ng the preaent memory cycle is also a memory cycle, it, too, is completed pel ore the TMS9900 enters me how state The
maximum number of consecutive memory cycles is three.
Fig. 4 (continued)
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