Texas Instruments 99/4A - Page 33

Drivers are deactivated to prevent the input data from conflicting
with output data. Memory write makes use of — MEMEN also -WE both
active, and DBIN deactivated. Under these conditions the 9900
outputs on the address and data buses and holds these outputs for the
duration required by RAM.
CRU ALLOCATION
Of the available 4K of CRU bits, the first IK (addresses 0000
07FE) are used internally in the Home Computer. The second IK
(addresses 0800-0FFE) are reserved for future use. The last 2K
(addresses 1000 — 1FFFE) are reserved for the peripherals to be plugged
in the 1/0 port. A block of 128 CRU bits is assigned to each
peripheral as listed below.
TABLE 1 CRU ASSIGNMENTS
CRU
ADDRESSES A3 A4 A5 A6 A7 USE
0000 — OFFE
1000-1 OFE
1100-1 1FE
1200-12FE
1300 — 13FE
1400 — 14FE
1500 — 15FE
1600 — 16FE
1700 — 17FE
1800 — 18FE
1900-1 SEE
1F00-1FFE
0 X X
1 0 0
1 0 0
1 0 0
1 0 0
1 0*1
1 0 1
1 0 1
1 0 1
1 1 0
1 1 X
1 1 1
X
0
0
1
1
0
0
1
1
0
X
1
X
0
1
o
1
0
1
0
1
0
X
1
INTERNAL USE
RESERVED
DISK CONTROLLER
RESERVED
PRIMARY RS232
RESERVED
SECONDARY RS232
RESERVED
RESERVED
THERMAL PRINTER
FUTURE EXPANSION
P-CODE
INTERRUPT HANDLING
The interrupt available on
interrupts of the TMS 9901
the I/O port is one of the maskable
Programmable Systems Interface.
VECTOR LOC.
TABLE 2 9900 INTERRUPTS
INTERRUPT
LEVEL
(MEMORY ADDR.
IN HEX)
CPU
PIN
DEVICE
ASSIGNMENT
(HIGHEST 0
0000
RESET
RESET
PRIORITY) 1
FFFC
LOAD
LOAD
0004
INTI
EXT DEV (9901)
Lower priority CPU interrupt are not used. The additional interrupts
available are implemented on the 9901.
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