Texas Instruments 99/4A - Page 48

16 TO 8 BIT INTERFACING CIRCUIT.
GENERAL DESCRIPTION
The 16 to 8 bit interfacing circuit is used to interface 8 bit
devices such as Video Display Processor (VDP) . The sound chip,
graphics-read-only memory (GROM) and external 8 bit peripherals to
the 16 bit data bus of the TMS 9900. It does so bv successively
placing the least significant and most significant byte of a word
on the 8 bit system data bus during a write operation. During a
read operation adjacent bytes are placed in the least significant
and most significant byte of the 16 bit word. To enable 8 bit
devices to destinguish between the bytes, an additional address
line A15 is generated. The interfacing circuit also performs the
synchronization between devices connected to the 8 bit system data
bus and the TMS 9900 by generating adequate timing of WE and READY
signals. A schematic of the interfacing circuit is given in
figure 13, p. 41.
HARDWARE DESCRIPTION
The hardware description is divided in the following parts:
A.
B.
C.
D.
Description of the 16 to 8 bit multiplexing circuit.
Generation of the control signals for the multiplexing .
ci rcui t .
READY/HOLD generati on .
WE generation.
A. 16 TO S BIT MULTIPLEXING CIRCUIT
An overview of the hardware used to interface the 16 to 8 bit
data uses is given in figure 13, p. 41. During a write operation
the data on the 16 bit bus is gated to the 8 bit system bus by
enabling U616 and U614 in succession. During a read operation the
least significant byte on the 8 bit data bus is stored in the 8.
bit latch U615. Then the most significant byte is gated to the 16
bit data bus by enabling bidirectional buffer U614 and the total
word is fetched by the TMS 9900. The DIOG and DBIN on U614, DING
and A15 on U615 and the DOG on U616 are used for enabling IC ? s and
_for determining the direction to the data flow if no interfacing
occurs, the 16 bit data bus is kept floating to allow the TMS 9900
to access ROM or RAM memory.
B. CONTROL SIGNAL GENERATION
Control signals for the multiplexing circuit are generated by the
circuit in figure 14, p. 42. U613 is a 4 bit shift register the
outputs of which are used for timing purposes. When the START
signal is high, pin 2 of U604 is low. This pin, connected to pin
1 of U613, sets all the outputs of the shift register to a binary
zero. Since the START signal is also connected to pin 10, the
shift register is disabled. Control signal generation is started
when START becomes low, pin 10 which also becomes low selects the
shift right mode of shift register U613. Shift operation is then
started as soon as pin 9 of U613 becomes high, depending on the
system ready status. When the shift operation has begun shift
output QC on pin 13 inverted in U602 and feedback to the shift
right input on pin 2. On every rising flank of QI (pin 11) the
contents of the shift registers are shifted one position, giving