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Texas Instruments 99/4A - Page 49

Texas Instruments 99/4A
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timing
signals
on
the
outputs
GA,
QB,
and
DC
(see
-Figures
17-1S,
p.
45-46).
These
outputs
are
used
for
generating
the
control
signals
in
NAND-gates
U603
and
U606.
Both
DBIN
and
DE'IN
are
used
tor
selecting
the
direction
o-F
the
data
-Flow.
CSVDPR
disables
U614
if
a
read
from
the
video
display
processor
occurs,
because
the
VDP
data
bus
is
directly
connected
to
D1-D7
of
the
TNS
9900.
C.
READY
GENERATION
The
READY
generation
circuit
as
shown
in
figure
15,
p.43
has
two
operating
modes.
In
the
normal
mode
the
system
ready
signals
is
input
on
pin
12
of
U607.
The
pull-up
resistor
R50S
assures
that
under
normal
circumstances
the
READY
signal
is
true.
Slow
devices
can
add
wait
states
by
pulling
pin
12
of
U607
to
ground.
The
READY
signal
is
sampled
on
02
and
available
on
pin
9
of
U607.
THERE
ARE
NOW
TWO
POSSIBILITIES:
ROM
OR
RAM
IS
SELECTED
In
this
case
shift
register
U613
is
not
enabled
and
the
READY
signal
is
gated
directly
via
U603
and
U602
to
the
READY/HOLD
input
of
the
TMS
9900.
Note
that
in
this
case
pin
12
of
U603
has
to
be
high.
EXTERNAL
READY
TIMING
If
other
devices
then
ROM
or
RAM
are
selected,
the
16
to
S
bit
interfacing
circuit
will
be
used.
This
means
that
the
TMS
9900
has
to
be
put
in
a
WAIT
state
until
two
bytes
of
data
are
written
or
read
by
the
interfacing
circuit.
This
is
accomplished
by
decoding
the
GA
and
0C
outputs
of
the
shift
register
in
NAND-gates
U612
and
0603
to
provide
a
low
READY
signal
until
both
bytes
are
processed
by
the
interfacing
circuit.
If
during
this
operation
a
device
generates
a
not
READY,
the
shi'ft
register
will
stop
its
operation
until
ready
becomes
high
again.
Timing
diagrams
for
the
READY
signal
can
be
seen
in
figures
7
—
8,
p
.27
—
28.
WE
GENERATION
The
WE
circuit
as
given
in
figure
16^.p44
generates
the
WE
signals
when
writing
data
to
an
external
device.
In
that
case
WE
of
the
system
has
to
be
low
every
time
a
byte
of
information
is
transferred.
To
accomplish
this
,
outputs
QB,
on
pin
14
and
00
on
pin
13
of
U613
are
used
to
set
and
preset
flip
flop
0607
on
pin
2
and
4.
In
this
way
two
periods
of
2
clock
cycles
long
for
which
WE
is
low
are
generated
on
pin
3
of
U606.
Q4,
which
is
in
agreement
with
TMS
9900
timing.
WE
is
only
gated
to
external
devices
when
a
memory
write
is
accomp
1
ishesd
by
combining
the
WE
of
the
TMS
9900
after
inverting
in
0602
with
the
WE
of
the
interfacing
circuit.
The
total
signal
is
then
available
of
pin
3
40

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