Texas Instruments 99/4A - Page 57

graphic read only memory
GENERAL DESCRIPTION
The TMC 0430 GROM is a P-channel
8 — bit bytes. The circuit has an
counter which selects one of the
read only memory containing 6144
on chip autoincrementing address
6144 memory bytes.
FUNCTIONAL DESCRIPTION
CPU INTERFACE
The GROM interfaces to the CPU through the parallel data bus and
the memory control lines as shown in figure 52, p. 132. The CPU
interface consists of 8 data I/O lines (D0-D7) , chip enable (CE) ,
READY, and 2 mode'Control lines (MO, Ml). The GROM also requires
a nominal SOO KHz clock input (OSC) .
GROM PAGING
The GROM has a 16-bit address register of which the lower 13-bits
are used to address the 6144-byte ROM matrix. The most
significant field is used to select one of eight GROM pages. Each
GROM has a fixed 3 — bit page number which is determined during
manufacture. The GROM compares this number with the address
register page select field. If a match occurs, then the GROM is
the "selected page" or "current page". The GROM data bus is
placed into the output mode during a read data operation only if
the GROM is the current page. The other GROM functions are not
affected by the page select field. The page select field permits
up to eight GROMs to be used in parallel. Each GROM is tied to
the same chip enable, memory control, and data lines as the other
GROMs. Since the page select field does not affect the data
register or address register operations, all parallel GROMs are
synchronized following initialization. However, since only one
GROM is the current page, only one GROM outputs data on the data
bus during a read data operation. If no GROM is selected (the
address register page field does not match the page number of any
GROM), then no GROM is placed into the output mode during a read
data operation. During a read address operation, all GROMs output
the address byte. Since all GROMs are synchronized following
initialization no data bus conflict occurs.
ADDRESS REGISTER AUTOINCREMENTATION
The address counter is autoincremented following a read, data,
write data, or a pair of consecutive write address operations.
When the current address is 8191, the next autoincrement cycle
will result in a zero address value. The page select field is not
affected by the autoincrement .
When the value of the address register lower 13-bit field is
greater that 6143, the GROM will continue to fetch data from the
6144 byte array. This condition should be avoided in order to
prevent invalid data fetches and transfers.
INITIALIZATION
During the power up sequence, the microprocessor should execute a
"dummy" read data operation. This will guarantee that a newly
powered up GROM will not respond to the first write address
operation as if the were the second write address operation. The
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