Texas Instruments 99/4A - Page 58

microprocessor should then initialize the GROM address registers
with two consecutive write-address operations.
The GROM ready line is normally low and is high only when the GROM
has an active CE and has read in the contents of the data bus
during a write operation or has placed data on the bus during a
read operation. The READY line control is independent of the
page select. Typical READY line timing is shown in figure 21, p.
ACCESS DELAY
The GROM requires that a second I/O operation not occur before it
has completed the first operation. Consequently, CE must remain
high at least 2.5 GROM clock cycles following the trailing edge of
the last I/O operation. For a minimal 500 kHz OSC input, th'e
minimal required delay between the rising edge of CE and the next
falling edge is 5 microseconds.
I/O OPERATIONS
When CE becomes active (low), the mode lines determine which one
of four GROM I/O operations is to occur as shown in Table 6.
TABLE 6 GROM I/O OPERATIONS
MODE
MO Ml I/O OPERATION
0 0 WRITE DATA - The write data operation is included for use
in future read/write versions of the GROM. The write data
operation does not result in a data transfer to the TMC
0430 GROM. The address register is then autoincremented .
The addressed ROM byte is fetched and placed into the GROM
data register.
O 1 READ DATA - The read data operation transfers the data
byte in the data register to the CPU if the GROM is the
current page. The address register is then autom-
cremented. The addressed ROM byte is fetched and placed
into the GROM data register.
1 0 WRITE ADDRESS - The write address operation transfers the
data byte on the GROM data I/O bus to the least signi 
ficant byte (LSB) of the GROM address register. The old
address register (LSB) is transferred to The address
register most significant byte (MSB). Two consecutive
write address operations cause the addressed ROM byte to
be fetched and placed into the GROM data register; the
address register is then autoincremented . A write address
operation immediately following a read data, read address,
or write data operation does not result in a data fetch
and address autoincrementation .
1 1 READ ADDRESS — The read address operation transfers the
MSB of the address register to the CPU if the GROM is the
current page. The address register LSB is automatically
transferred to the MSB.
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