Texas Instruments 99/4A - Page 59

It should be noted that the NO line controls whether the data or
address register is to be aHected and the Ml line controls
whether the operation is an input or output cycle.
HARDWARE DESCRIPTION
The 99/4 has three internal GROMs (TMC 0430) and the possibility
to add 5 more external GROMs via the GROM port. All GROMs are
connected in parallel as can be seen in -Figure 52, p.132.
GROM CLOCK
The clock signals tor the GROMs are derived from the TMS 9918
video display processor. The clock cycle time is 2.24 usee. A IK
ohm pull-up resistor is used to ensure proper -Functioning of the
P-channel device with TTL logic.
DATA BUS INTERFACING
All GROMs are connected in parallel to the 8 bit data bus.
MODE CONTROL
The type o-F operation performed by the GROM is determined by
connections DBIN to Ml and address line A14 to MO. Thus a read
operation is performed when DBIN is high and a write operation
when DBIN is low. Address line A14 distinguishes between data and
address operations.
GROM SELECT
GROM select is performed by the circuit in figure 20, p 52. When
MEMEW is low, U504 decodes address lines AO, Al and A2. Decoder
output Y4 is used to select a second 3 to 8 decoder U505. This
device is enabled when A15 and one or both signals DBIN and A5 are
low. Decoding of address lines A3, A4 and A5 are then used to
select the GROMs by "ANDing" outputs Y6 and Y7 by means of the
NAND U506 and inverter U508.
GROM READY
The GROM ready signal is connected to the READY/HOLD via U508 and
U506. U508 inverts the GROM READY signal. This signal is then
combined in NAND — GATE U506 with the GROM select signal to get the
appropriate signal for the system READY/HOLD line.
MEMORY MAP
Table 7 shows the memory map for the successive GROM instructions.
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