Texas Instruments 99/4A - Page 63

TMb 9'901 PROGRAMMABLE SYSTEM INTERFACE
GENERAL DESCRIPTION
The TMS 9901 is a programmable system inter-Face (PSI), which can
be used -For input, output and interrupt priority handling. It
also -features an on chip programmable interval timer. The TMS
9901 is used -for keyboard, remote handheld control unit, cassette
recorder i n t er f ac i ng and VDP interrupt handling in the 99/4A
system .
The TMS 9901 PSI inter-Faces to the CPU through the Communicati on
Register Unit (CRU) and the interrupt control lines. The TMS 9901
occupies 32 bits of CRU input and output and space. The five
least significant bits of the address bus are connected to the PSI
to address one of the 32 CRU bits of the TMS 9901. The most
significant bits of the address bus are decoded on CRU cycles to
select the PSI by taking its chip enable (CE) .line active (low).
Interrupt inputs to the TMS 9901 PSI are sychronized with 03,
inverted, and then ANDed with the appropriate mask bit. Once
every 03 clock time, the prioritizer looks at the 15 interrupt
input AND gates & generates the interrupt control code. The
interrupt control code and the interrupt request line constitute
the interrupt interface to the CPU.
After reset all I/O ports are programmed as inputs. By writing to
any I/O port, that port will be programmed as an output port until
another reset occurs, either software or hardware. Data at the
input pins are buffered on the TMS 9901. Data to the output ports
in latched and then buffered on-chip by the PSI ’ s MOS to TTL
buff ers .
The interval timer on the TMS 9901 is accessed by writing a one to
select bit zero (control bit) which puts the PSI CRU interface in
the clock mode. Once in the clock mode the 114 bit clock contents
can be read or written. Writing to the clock register will
reinitialiize the clock and cause it to start decrementing. When
the clock counts to zero, it will cause interrupt and reload to
its initial value. Reading the clock contents permits the user to
see the derementer contents at the point in time just before
entering the clock mode. The clock read register is not updated
when the PSI is in the clock mode. A block diagram of the TMS
9901 PSI is given in figure 25, p.62.
CRU INTERFACE
The CPU communicates with the TMS 9901 PSI via the CRU. The TMS
9901 occupies 32 bits in CRU read space and 32 bits in CRU write
space. The CRU interface consist of 5 address select lines
(S0-S4) , chip enable (CE) , and three CRU lines (CRUIN, CRUOUT,
CRUCLK) . The select lines (S0-S4) are connected to the five least
significant bits of the address bus (A10-A14). Chip enable (CE)
is generated by decoding the most significant bits of the address
bus on CRU cycles: When CE goes active (low), the five selected
lines point to the CRU bit being accessed. Whin CE is inactive
(high), the PSI's CRU interface is disabled. In case of a write
operation, the TMS 9901 strokes data off the CRUOUT line with
CRUCLK. For read operation, the data is sent to the CPU on the
CRUIN line.
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