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Texas Instruments 99/4A - Page 75

Texas Instruments 99/4A
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T
E
L
E
VISI
□
N
£
CREE
N
DIE
P
L
A
¥
The
VDP
assembles
three
major
elements
into
a
composite
for
displav
on
the
target
television:
background,
pattern
matrix,
and
sorites.
In
normal
operation
the
b
a
c
k
g
r
o
u
n
d
is
composed
of
the
b
o
r
d
e
r
of
the
active
display
area.
The
color
of
this
region
is
specified
bv
loading
the
specific
code
for
the
color
desired
into
the
screen
background
color
register.
All
color
of
this
region
is
specified
by
loading
the
specific
code
for
the
color
desired
into
the
screen
background
color
register.
All
color
information
is
described
by
four
bit
codes
composed
of
three
color
select
bits
and
an
intensity
bit
giving
a
total
range
of
15
colors
with
one
code
reserved
for
the
transparent
state.
PATTERN
GENERATION
The
second
element
of
the
screen
display
is
the
32X24
matrix
of
patterns
formed
and
is
the
active
display
area.
Each
pattern
is
composed
of
an
6x8
matrix
of
picture
elements.
In
a
raster
scanned
television
system
each
line
of
video
information
must
be
built
and
displayed.
To
accomplish
this,
a
list
of
733
8-bit
names
—
one
for
each
pattern
to
be
displayed
—
is
assembled
in
the
screen
refresh
memory.
The
8-bit
name
contains
both
color
and
display
information
.
EXTERNAL
VIDEO
OPERATION
In*
this
mode
any
VDP
-
generated
signal,
other
than
the
background,
will
be
displayed
as
generated.
When
no
signal
is
generated,
the
external
signal
is
gated
through.
In
both
modes,
however,
the
external
sync,
blanking,
and
color
burst
signals
are
controlling
the
VDP
and
the
target
TV
system.
No
internal
synchronization
is
made
to
the
color
burst.
Therefore,
if
a
color
VDP
generated
signal
is
desired,
an
externally
generated
10.7
NHz
(
i.e.,
3
x
the
color
frequency
)
must
be
provided
to
the
XTL1
input
and
its
non-over
lapping
compliment
to
the
XTL2
input.
VDP
RESET
The
VDP
is
reset
by
applying
a
low
signal
to
the
REET
pin.
This
signal
must
last
for
at
least
2
usee.
Reset
does
the
following:
synchronizes
aid
clocks
to
its
negative
going
edge
(
this
includes
01-04
control
clocks,
CPUCLK,
GRONCLK
and
color
burst),
sets
horiz
ontal
and
vertical
counters
to
a
known
state,
clears
the
internal
command
register,
gets
the
text
color
and
boarder
color
to
black,
and
clears
all
status
flags.
POWER
UP
VEE
must
be
applied
to
the
4116s
either
before
or
at
the
same
time
as
the
other
supplies
and
removed
last.
Failure
to
observe
this
precaution
will
cause
dissipation
in
excess
of
the
absolute
maximum
ratings
due
to
internal
forward
bias
conditions.
Thi-s
also
applies
to
system
use,
where
failure
of
the
VEE
supply
must
immediately
shut
down
the
other
supplies.
After
power
up,
eight
memory
cycles
must
be
performed
to
achieve
proper
device
operation.

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