Texas Instruments 99/4A - Page 76

m a p n kj a p p DES C FIP TI □ h i
OSCILLATOR CIRCUITRY
An overview of the
-f i gur e 29, o7 1 -
connections
to the
THS 99 IS VDP are given in
Timing signals For the THS 9918 are derived from an on-chip
oscillator which uses an external 10=7 MHz crystal , This crystal
(¥100) in series with L100 is connected between pin 39 and 40..
L100 is adjustable to set the frequency. C100 and C101 are ths
capacitors in the frequency determining network. RIOT is added
in parallel to ¥100 and LI 00 to lower the impedance of the network,
thus assuring a proper voltage swing at pin 39. Also a 5 volt
voltage is fed to pin 39, (R102 and L107 for decoupling). This
voltage is used for proper start-up of the oscillator.
POWER CONNECTIONS
The TMS 991S uses only one power supply voltage. Fin 12 (VSS)- is
connected to the system ground, and PIN 33 (VCC) to the +5 volt
power supply. C102, C103, C104 and L101 are used to suppress noise
on the 5 volt line.
GROM CLOCK
The 10.7 MHz oscillator frequency is internally divided by 24.
This gives a frequency of 445.8 KHz. This frequency is buffered
and fed to pin 37 and used as the GROM clock.
CPU CLOCK
The 3.58 MHz CPU clock on PIN 38 is used by TMS 9919 sound
processor (on units which use the SN 76489).
RESET
The TMS 9918 is reset during power up or with a solid state soft 
ware command module by using the reset signal of U601 pin 4. This
signal is monitored by the 9913 on pin 34.
CHIP SELECTION LOGIC
The VDP is selected with CSW on pin 14 or CSR on pin 15 are low
When CSW is low the microprocessor can
is low, data can be read from the VDP.
is used io combination with CSW and CSR
of operation.
write to the VDP, when CSR
The MODE signal on pm 13
to select four basic modes
The selection logic which enables CSW or CSR is given in figure
p6W ’ '
Selection pins ¥2 ( pin 13 ) and Y13 (pin 12)
used to distinguish between a write or read
selection from pin 12 is combined with the
of U505 (74LS1 38) are
operation. The write
WE signal in OR-gate
U507. Thus only a VDP write can occur when WE is low..
DATA BUS INTERFACING
Pins 17 through 24 (data lines CDQ through CD7) are directlv con 
nected to DO through D7 of the TMS 9900.