Texas Instruments 99/4A - Page 91

T hITFPQijPT H £ j-Jnl_ T M □
The interrupt available on the I/O pert is one of the maskable
interrupts of the THS 9901 programmab 1 e svstems interface-
PURFERIMG
All I/O signals must be able to drive two LG — tvoe loads (with the
exception of the data bush In addition., peripherals generating
CRUIN, READY/HOLD, LOAD and EXT INT shall buffer these signals be 
fore putting them on the I/O bus.
I/O READ
A CPU read cycle -for the external device consists of two 8 — bit
read cycles (-figure 18, p48) . The two bytes read are assembled as
a 18 bit word before they are presented to the 9900.
MEMEN goes low true at the beginning of clock
cycle 1.
the
same time DEIN g
entire cycle. At
bus goes active,
(associated with
oes high true,
the same time
In order -for
crosstalk and
WE stays high false during the
that MEMEN goes true, the address
the noise and the glitches
simultaneous switching) to go away.
we allow a minimum of IDO ns for the address lines to settle. MEE
(see memory selection logic) goes true during the leading edge of
02 of clock cycle 1. Data read from the peripherals will be valid
750 ns after the start of clock cycle 1. The CPU will look at the
full 18 bit data bus during the leading edge of 0.1, of clock cvcle
2. Under worst-case conditions, data must be valid 100 ns before
that time.
I/O WRITE
Figure 17,p45 shows a 18 bit I/O write cycle. As described earlier
it is composed of two 8-bit writes. A write cycle will always be
preceded by an ALU cycle. MEMEN and DBIN go true at the start of
the cycle. A settling time of 100 ns (minimum) is allowed for the
address lines to settle down. WE goes true (low) on the leading
edge of 02, during the wait states, and stays true for 880 ns
(typically). During a read and a write, the odd byte is accessed
first, followed by an even byte. A15/CRU out changes its state 99G
ns (typically after the cycle is initiated. The second 8-bit write
cycle is identical to the first 8-bit write. MEE stays true (low)
during the entire (1.8 usee) cycle.
SPEECH INTERFACE
The I/O port has 4 lines dedicated for use by ths speech module:
+5, -5, speech block enable (SEE) and audio in. SEE is decoded by
the 99/4A for addresses 9000 and 9400 (write and read) . For the
write cycle, SEE goes active after ths address and data lines are
valid.
GROM INTERFACE ON I/O PORT
All signals are provided to use GROM'S in external devices. Decode
for GROM select must be performed in the external device.