Texas Instruments 99/4A - Page 92

CRU TIMING
CRU interface timing i s shewn in figure 10, p30. The CRUGUT cycle
is composed of 2 clock cycles. The CRU bit address when placed on
the address bus AG through A14 is allowed to settle for 100 ns
(minimum) . CRUCLK is a So ms low true signal which occurs on the
trailing edge of 01, of clock cycle 2. CRUGUT data is valid at
ths start of clock cycle, and is latched by the CRUCLK in the re-
pective peripheral. CRUIN also consists of 2 clock cvcles of 660
ns ( t yp i ca 1 1 v j . Anai n we allow 1 UO ns f or the a. d d r e ss bus to
settle down. The CPU samples the CRUIN line on the leadinc sdce of
U 1 ot cycle 2. Data must be valid 40 ns (min) before thatu
HARDWARE DESCRIPTION
An overview of the hardware used
signals on the 1/0 bus is given in
to buffer the IN and
figures 55, pl 35 and 51,
OUTPUT
p!31.
ADDRRESS BUS BUFFERING
U503, U509
Al 4. U510
signal has
1 i ne .
and U510 are used to buffer address lines A0 through
is only used for A0, Al, A2 and A15/CRU0UT. This last
a series resistor R512 to reduce transients on the
WE is buff er ed b y U5 10
R505 is used to reduce
on the output
transi ents .
(pin 10).
A series resistor
CRUCLK
The CRUCLK signal from the 99/4A
fered by U510. Again a series
transients. The buffered signal
in inverted in U602 and then buf-
resistor R507 is used to reduce
is also used on the GROM port.
03
03 is buffered by U510, R506 used to reduce transients.
MBE
MBE is buffered by U5 10.
D B I N
DBIN is buffered by the two inverters U50S.
Since the data bus in buffered by U616 in the interfacing circuit,
no additional buffering is necessary. However to meet loading re-
quirements- a special pull-up/pull down circuit is added. When DBIN
is low, 0500 is in the on state.
R519 is used to reduce the base current in 0500. When in the on
state, resistor pack R500 is connected to ground, thus generating
a pull-down. When DBIN is low. 0500 is disabled. CR501, R520.
R521, CR502 and R522 compose a circuit which gives- a voltage of 5
volts to the resistor pack. Thus a pull-up exists when DBIN is
1 ow .
OUTPUT BUS PIN CONNECTIONS
An overview of the 1/0 bus pm connections is given on pl04.