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Texas Instruments TMS320C67X - Page 348

Texas Instruments TMS320C67X
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Pipeline Execution of Instruction Types
Pipeline4-16 SPRU733
4.2.1 Single-Cycle Instructions
Single-cycle instructions complete execution during the E1 phase of the pipe-
line (see Table 43). Figure 48 shows the fetch, decode, and execute phases
of the pipeline that single-cycle instructions use.
Figure 49 shows the single-cycle execution diagram. The operands are read,
the operation is performed, and the results are written to a register, all during
E1. Single-cycle instructions have no delay slots.
Table 43. Single-Cycle Instruction Execution
Pipeline Stage
E1
Read src1
src2
Written dst
Unit in use
.L, .S., .M, or .D
Figure 48. Single-Cycle Instruction Phases
PG PS PW PR DP DC E1
Figure 49. Single-Cycle Instruction Execution Block Diagram
(data)
Operands
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Register file
Write results
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Functional
unit
.L, .S, .M,
or .D
E1