EasyManua.ls Logo

Texas Instruments TMS320C67X - Page 383

Texas Instruments TMS320C67X
465 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Functional Unit Constraints
4-51PipelineSPRU733
Table 4−35 shows the instruction constraints for ADDDP/SUBDP instructions
executing on the .L unit.
Table 4−35. ADDDP/SUBDP .L-Unit Instruction Constraints
Instruction Execution
Cycle 1 2 3 4 5 6 7 8
ADDDP/SUBDP R R W W
Instruction Type
Subsequent Same-Unit Instruction Executable
Single-cycle Xr Xw Xw
4-cycle Xr Xw Xw 
INTDP
Xrw Xw Xw 
ADDDP/SUBDP
Xr 
Instruction Type
Same Side, Different Unit, Both Using Cross Path Executable
Single-cycle Xr
DP compare Xr 
2-cycle DP
Xr 
4-cycle
Xr 
Load

Store

Branch
Xr 
16 × 16 multiply
Xr 
MPYI
Xr 
MPYID
Xr 
MPYDP
Xr
Legend: = E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction;
= Next instruction can enter E1 during cycle; Xr = Next instruction cannot enter E1 during cycle-read/
decode constraint; Xw = Next instruction cannot enter E1 during cycle−write constraint; Xrw = Next instruction cannot
enter E1 during cycle−read/decode/write constraint