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Texas Instruments TMS320C67X - Page 384

Texas Instruments TMS320C67X
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Functional Unit Constraints
Pipeline4-52 SPRU733
4.3.4 .D-Unit Instruction Constraints
Table 4−36 shows the instruction constraints for load instructions executing on
the .D unit.
Table 4−36. Load .D-Unit Instruction Constraints
Instruction Execution
Cycle 1 2 3 4 5 6
Load RW W
Instruction Type
Subsequent Same-Unit Instruction Executable
Single-cycle
Load 
Store

Instruction Type
Same Side, Different Unit, Both Using Cross Path Executable
16 × 16 multiply
MPYI 
MPYID

MPYDP

Single-cycle

DP compare

2-cycle DP

Branch

4-cycle

INTDP

ADDDP/SUBDP
Legend: = E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction;
= Next instruction can enter E1 during cycle