MT8206
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
June, 2006
Item Symbol Pin # Type Description
6 HDMISD2 AA23
1) GPIO (default, input in initial state)
2) CH 5/6 data input for HDMI
7 HDMISD3 AA24
1) GPIO (default, input in initial state)
2) CH 7/8 data input for HDMI
CCIR Interface (9)
1 CCIR_VCLK W23
1) GPIO (default, input in initial state)
2) CCIR656 clock input from external TVD
2 CCIR_V0 Y26
1) GPIO (default, input in initial state)
2) CCIR656 data0 input from external TVD
3 CCIR_V1 Y25
1) GPIO (default, input in initial state)
2) CCIR656 data1 input from external TVD
4 CCIR_V2 Y24
1) GPIO (default, input in initial state)
2) CCIR656 data2 input from external TVD
5 CCIR_V3 Y23
1) GPIO (default, input in initial state)
2) CCIR656 data3 input from external TVD
6 CCIR_V4 W26
1) GPIO (default, input in initial state)
2) CCIR656 data4 input from external TVD
7 CCIR_V5 W25
1) GPIO (default, input in initial state)
2) CCIR656 data5 input from external TVD
8 CCIR_V6 W24
1) GPIO (default, input in initial state)
2) CCIR656 data6 input from external TVD
9 CCIR_V7 V24
1) GPIO (default, input in initial state)
2) CCIR656 data7 input from external TVD
TTL Interface (4)
1 DE C6 O
1) GPIO (default, input in initial state)
2) Data enable, 2mA
2 VSYNCO B6 O Vertical sync, 2mA
3 HSYNCO A6 O Horizontal sync, 2mA
4 VCLK D6 O
Works in stand-by mode
1) GPIO (default, input in initial state)
2) Video output reference clock, 10mA
ANALOG (117)
PLL Group (12)
1 TP3 C23 I/O Positive PLL group test pin
2 TN3 D22 I/O Negative PLL group test pin
3 PLLVSS1 B23 GND PLL group ground