Toshiba 27D46 - Using the V-Chip (parental control) feature

SD DIGITAL MODULE BLOCK DIAGRAM
SD_DTV ASIC
IC2401
ZR39640BGCG-B1
16Mbit MOR FLASH
IC2408
SST39VF1681-70-EKE
8VSB/QAM/BTSC DEMOD.
IC2402
CAS-220/CS
256Mbit DDRSAM
IC2404
HY5DU561622DTP-D43
X2401
24.567MHz
X2402
25.000MHz
SIF AMP
WP
WE
ADR
DAT
+3.3V
RESET
16
1414
11
16
12
I2C1_DATA
I2C1_CLK
F/E_RESET
19
20
61
57
56
54
52
65
63
66
80
79
U7
M15
K2
J1
K15
R3
T2
R4
R5
U1
TS_DATA
TS_FRAME
TS_DVALID
TS_CLK
ADATA
WS
BCLK
+3.3V
L15
T1
J17
H17 U14
L3
K1
U17
N17
ADR
DAT
16
16
+2.6V
+2.6V
IFN
IFP
IF AGC
F/E+1.8V
SIF
TU I2C CLK
TU I2C DATA
SIF
RF_SW
SPDIF
C OUT Y OUT
SD-H
RX
TX
AFT(1)
AFT(0)
+3.3V
ASIC+1.8V
94 93 11 18
97
16
IF OUT2
34
IF OUT1
IF AGC
30
F/E+1.8V
29
SIF
28
RF SW
27
TU I2C CLK
26
TU I2C DATA
25
SPDIF OUT
24
NC
21
AUDIO-R
20
AUDIO-L
19
C OUT
18
Y OUT17
NC
16
SD-H
15
RESET
14
RX
13
TX
12
AFT(1)
11
AFT(0)
10
+3.3V
9
NC
6
ASIC+1.8V
5
+5V
2
+2.6V
1
NC
(CP2403
33
NC
NC
N1
RESET
AUDIO DAC
IC2501
CS4345-CZZ
T4
R2
R6
T3
BCLK
WS
ADATA
SCLK
9
10 7
+5V
2
314
OPE AMP
IC2502
NJM4580V(TE1)
17
5
3
E-3 E-4