Toshiba TX49 TMPR4937

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64-Bit TX System RISC

TX49 Family

TMPR4937

Rev. 2.0

Main Page

Table of Contents5
Tmpr493743
Overview and Features47
Overview47
Features47
Features of the TX49/H3 Core48
Features of TX4937 Peripheral Functions48
Configuration53
TX4937 Block Diagram53
Signals55
Pin Signal Description55
Signals Common to SDRAM and External Bus Interfaces55
SDRAM Interface Signals56
External Interface Signals57
DMA Interface Signals58
PCI Interface Signals58
Serial I/O Interface Signals60
Timer Interface Signals60
Parallel I/O Interface Signals60
AC-Link Interface Signals61
Interrupt Signals61
Extended EJTAG Interface Signals62
Clock Signals62
Initialization Signal63
Test Signals63
Power Supply Pins63
Boot Configuration64
Pin Multiplex68
Address Mapping69
TX4937 Physical Address Map69
Register Map70
Addressing70
Ways to Access to Internal Registers70
Configuration Registers81
Detailed Description81
Detecting G-Bus Timeout81
Registers82
Chip Configuration Register (CCFG) 0Xe00083
Chip Revision ID Register (REVID) 0Xe00886
Pin Configuration Register (PCFG) 0Xe01087
Timeout Error Access Address Register (TOEA) 0Xe01890
Clock Control Register (CLKCTR) 0Xe02091
G-Bus Arbiter Control Register (GARBC) 0Xe03093
Clocks95
TX4937 Clock Signals95
Power-Down Mode99
Halt Mode and Doze Mode99
Power Reduction for Peripheral Modules99
Power-On Sequence100
External Bus Controller101
Features101
Block Diagram102
Detailed Explanation103
External Bus Control Register103
Global/Boot-Up Options104
Address Mapping105
External Address Output106
Data Bus Size107
Access Mode109
Access Timing113
Clock Options119
Register120
0X9010 (Ch. 2), 0X9018 (Ch. 3) 0X9020 (Ch. 4), 0X9028 (Ch. 5) 0X9030 (Ch. 6), 0X9038 (Ch. 7)121
Timing Diagrams124
ACE* Signal125
Normal Mode Access (Single, 32-Bit Bus)127
Normal Mode Access (Burst, 32-Bit Bus)131
Normal Mode Access (Single, 16-Bit Bus)133
Normal Mode Access (Burst, 16-Bit Bus)137
Normal Mode Access (Single, 8-Bit Bus)139
Normal Mode Access (Burst, 8-Bit Bus)142
Page Mode Access (Burst, 32-Bit Bus)144
External ACK Mode Access (32-Bit Bus)146
READY Mode Access (32-Bit Bus)152
Flash ROM, SRAM Usage Example154
DMA Controller157
Features157
Block Diagram158
Detailed Explanation160
Transfer Mode160
On-Chip Registers161
External I/O DMA Transfer Mode161
Internal I/O DMA Transfer Mode164
Memory-Memory Copy Mode165
Memory Fill Transfer Mode165
Single Address Transfer165
Dual Address Transfer168
DMA Transfer173
Chain DMA Transfer174
Dynamic Chain Operation176
Interrupts177
Transfer Stall Detection Function177
Arbitration Among DMA Channels178
Restrictions in Access to PCI Bus178
DMA Controller Registers179
DMA Master Control Register (DM0MCR, DM1MCR)181
DMA Channel Control Register (Dm0Ccrn, Dm1Ccrn)183
DMA Channel Status Register (Dm0Csrn, Dm1Csrn))187
DMA Source Address Register (Dm0Sarn, Dm1Sarn)189
DMA Destination Address Register (Dm0Darn, Dm1Darn)190
DMA Chain Address Register (Dm0Charn, Dm1Charn)191
DMA Source Address Increment Register (Dm0Sairn, Dm1Sairn)192
DMA Destination Address Increment Register (Dm0Dairn, Dm1Dairn)193
DMA Count Register (Dm0Cntrn, Dm1Cntrn)194
DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR)195
Timing Diagrams196
Single Address Single Transfer from Memory to I/O (32-Bit ROM)196
Single Address Single Transfer from Memory to I/O (16-Bit ROM)197
Single Address Single Transfer from I/O to Memory (32-Bit SRAM)198
Single Address Burst Transfer from Memory to I/O (32-Bit ROM)199
Single Address Burst Transfer from I/O to Memory (32-Bit SRAM)200
Single Address Single Transfer from Memory to I/O (16-Bit ROM)202
Single Address Single Transfer from I/O to Memory (16-Bit SRAM)203
Single Address Single Transfer from Memory to I/O (32-Bit Half Speed ROM)204
Single Address Single Transfer from I/O to Memory (32-Bit Half Speed SRAM)205
Single Address Single Transfer from Memory to I/O (64-Bit SRAM)206
Single Address Single Transfer from I/O to Memory (64-Bit SDRAM)207
Single Address Single Transfer from Memory to I/O of Last Cycle When DMADONE* Signal Is Set to Output208
Single Address Single Transfer from Memory to I/O (32-Bit SDRAM)209
Single Address Single Transfer from I/O to Memory (32-Bit SDRAM)210
External I/O Device - SRAM Dual Address Transfer211
External I/O Device - SDRAM Dual Address Transfer213
External I/O Device (Non-Burst) - SDRAM Dual Address Transfer215
SDRAM Controller217
Characteristics217
Block Diagram218
Detailed Explanation219
Supported SDRAM Configurations219
Address Mapping220
Initialization of SDRAM225
Initialization of Memory Data, Ecc/Parity226
Low Power Consumption Function227
Bus Errors228
Memory Read and Memory Write228
Slow Write Burst228
Clock Feedback228
Ecc229
Registers233
0X8018 (Ch. 3)234
SDRAM Timing Register (SDCTR) 0X8040236
SDRAM Command Register (SDCCMD) 0X8058238
ECC Control Register (ECCCR) 0Xa000239
ECC Status Register (ECCSR) 0Xa008241
Timing Diagrams242
Single Read (64-Bit Bus)242
Single Write (64-Bit Bus)244
Burst Read (64-Bit Bus)246
Burst Write (64-Bit Bus)247
Burst Write (64-Bit Bus, Slow Write Burst)248
Single Read (32-Bit Bus)249
Single Write (32-Bit Bus)251
Low Power Consumption and Power down Mode253
SDRAM Usage Example258
PCI Controller259
Features259
Overall259
Initiator Function259
Target Function260
PCI Arbiter260
PDMAC (PCI DMA Controller)260
Block Diagram261
Detailed Explanation262
Terminology Explanation262
On-Chip Register262
Supported PCI Bus Commands264
Initiator Access (G-Bus → PCI Bus Address Conversion)266
Target Access (PCI Bus → G-Bus Address Conversion)268
Post Write Function270
Endian Switching Function270
66 Mhz Operation Mode271
Power Management272
PDMAC (PCI DMA Controller)273
Error Detection, Interrupt Reporting276
PCI Bus Arbiter278
PCI Boot280
Set Configuration Space281
PCI Clock281
PCI Controller Control Register282
ID Register (PCIID) 0Xd000284
PCI Status, Command Register (PCISTATUS) 0Xd004285
Class Code, Revision ID Register (PCICCREV) 0Xd008288
PCI Configuration 1 Register (PCICFG1) 0Xd00C289
P2G Memory Space 0 PCI Lower Base Address Register (P2GM0PLBASE) 0Xd010290
P2G Memory Space 0 PCI Upper Base Address Register (P2GM0PUBASE) 0Xd014291
P2G Memory Space 1 PCI Lower Base Address Register (P2GM1PLBASE) 0Xd018291
P2G Memory Space 1 PCI Upper Base Address Register (P2GM1PUBASE) 0Xd01C292
P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0Xd020292
P2G I/O Space PCI Base Address Register (P2GIOPBASE) 0Xd024293
Subsystem ID Register (PCISID) 0Xd02C294
Capabilities Pointer Register (PCICAPPTR) 0Xd034295
PCI Configuration 2 Register (PCICFG2) 0Xd03C296
G2P Timeout Count Register (G2PTOCNT) 0Xd040297
G2P Status Register (G2PSTATUS) 0Xd080298
G2P Interrupt Mask Register (G2PMASK) 0Xd084299
Satellite Mode PCI Status Register (PCISSTATUS) 0Xd088300
PCI Status Interrupt Mask Register (PCIMASK) 0Xd08C301
P2G Configuration Register (P2GCFG) 0Xd090302
P2G Status Register (P2GSTATUS) 0Xd094304
P2G Interrupt Mask Register (P2GMASK) 0Xd098305
P2G Current Command Register (P2GCCMD) 0Xd09C306
PCI Bus Arbiter Request Port Register (PBAREQPORT) 0Xd100307
PCI Bus Arbiter Configuration Register (PBACFG) 0Xd104309
PCI Bus Arbiter Interrupt Mask Register (PBAMASK) 0Xd10C311
PCI Bus Arbiter Broken Master Register (PBABM) 0Xd110312
PCI Bus Arbiter Current Grant Register (PBACGNT) 0Xd118314
PCI Bus Arbiter Current State Register (PBACSTATE) 0Xd11C315
G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 0Xd120317
G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 0Xd128318
G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE) 0Xd130319
G2P I/O Space G-Bus Base Address Register (G2PIOGBASE) 0Xd138320
G2P Memory Space 0 Address Mask Register (G2PM0MASK) 0Xd140321
G2P Memory Space 1 Address Mask Register (G2PM1MASK) 0Xd144322
G2P Memory Space 2 Address Mask Register (G2PM2MASK) 0Xd148323
G2P I/O Space Address Mask Register (G2PIOMASK) 0Xd14C324
G2P Memory Space 0 PCI Base Address Register (G2PM0PBASE) 0Xd150325
G2P Memory Space 1 PCI Base Address Register (G2PM1PBASE) 0Xd158326
G2P Memory Space 2 PCI Base Address Register (G2PM2PBASE) 0Xd160327
G2P I/O Space PCI Base Address Register (G2PIOPBASE) 0Xd168328
PCI Controller Configuration Register (PCICCFG) 0Xd170329
PCI Controller Status Register (PCICSTATUS) 0Xd174332
PCI Controller Interrupt Mask Register (PCICMASK) 0Xd178334
P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE) 0Xd180335
P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE) 0Xd188336
P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE) 0Xd190337
P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 0Xd198338
G2P Configuration Address Register(G2PCFGADRS) 0Xd1A0339
G2P Configuration Data Register (G2PCFGDATA) 0Xd1A4340
G2P Interrupt Acknowledge Data Register (G2PINTACK) 0Xd1C8341
G2P Special Cycle Data Register (G2PSPC) 0Xd1Cc342
Configuration Data 0 Register (PCICDATA0) 0Xd1D0343
Configuration Data 1 Register (PCICDATA1) 0Xd1D4344
Configuration Data 2 Register (PCICDATA2) 0Xd1D8345
Configuration Data 3 Register (PCICDATA3) 0Xd1Dc346
PDMAC Chain Address Register (PDMCA) 0Xd200347
PDMAC G-Bus Address Register (PDMGA) 0Xd208348
PDMAC PCI Bus Address Register (PDMPA) 0Xd210349
PDMAC Count Register (PDMCTR) 0Xd218350
PDMAC Configuration Register (PDMCFG) 0Xd220351
PDMAC Status Register (PDMSTATUS) 0Xd228353
PCI Configuration Space Register356
Capability ID Register (Cap_Id) 0Xdc357
Next Item Pointer Register (Next_Item_Ptr) 0Xdd358
Power Management Capability Register (PMC) 0Xde359
Power Management Control/Status Register (PMCSR) 0Xe0360
Serial I/O Port361
Features361
Block Diagram362
Detailed Explanation363
Overview363
Data Format363
Serial Clock Generator365
Data Reception367
Data Transmission367
Flow Control368
Reception Data Status368
Reception Time out369
Software Reset369
Error Detection/Interrupt Signaling370
Multi-Controller System371
Registers372
Line Control Register 0 (SILCR0) 0Xf300 (Ch. 0) Line Control Register 1 (SILCR1) 0Xf400 (Ch. 1)373
Dma/Interrupt Control Register 0 (SIDICR0) 0Xf304 (Ch. 0) Dma/Interrupt Control Register 1 (SIDICR1) 0Xf404 (Ch. 1)375
Dma/Interrupt Status Register 0 (SIDISR0) 0Xf308 (Ch. 0) Dma/Interrupt Status Register 1 (SIDISR1) 0Xf408 (Ch. 1)377
Status Change Interrupt Status Register 0 (SISCISR0) 0Xf30C (Ch. 0) Status Change Interrupt Status Register 1 (SISCISR1) 0Xf40C (Ch. 1)379
FIFO Control Register 0 (SIFCR0) 0Xf310 (Ch. 0) FIFO Control Register 1 (SIFCR1) 0Xf410 (Ch. 1)380
Flow Control Register 0 (SIFLCR0) 0Xf314 (Ch. 0) Flow Control Register 1 (SIFLCR1) 0Xf414 (Ch. 1)381
Baud Rate Control Register 0 (SIBGR0) 0Xf318 (Ch. 0) Baud Rate Control Register 1 (SIBGR1) 0Xf418 (Ch. 1)382
Transmit FIFO Register 0 (SITFIFO0) 0Xf31C (Ch. 0) Transmit FIFO Register 1 (SITFIFO1) 0Xf41C (Ch. 1)383
Receive FIFO Register 0 (SIRFIFO0) 0Xf320 (Ch. 0) Receive FIFO Register 1 (SIRFIFO1) 0Xf420 (Ch. 1)384
Timer/Counter385
Features385
Block Diagram386
Detailed Explanation387
Overview387
Counter Clock387
Counter388
Interval Timer Mode388
Pulse Generator Mode390
Watchdog Timer Mode391
Registers393
Timer Interrupt Status Register N (Tmtisrn) TMTISR0 0Xf004 TMTISR1 0Xf104 TMTISR2 0Xf204395
TMCPRA2 0Xf208396
Compare Register Bn (Tmcprbn) TMCPRB0 0Xf00C TMCPRB1 0Xf10C397
TMITMR2 0Xf210398
Pulse Generator Mode Register N (Tmpgmrn) TMPGMR0 0Xf000 TMPGMR1 0Xf130400
Watchdog Timer Mode Register N (Tmwtmrn) TMWTMR2 0Xf240401
TMTRR2 0Xf2F0402
Parallel I/O Port403
Characteristics403
Block Diagram403
Detailed Description404
Selecting PIO Pins404
General-Purpose Parallel Port404
Registers404
PIO Output Data Register (PIODO) 0Xf500405
PIO Input Data Register (PIODI) 0Xf504405
PIO Direction Control Register (PIODIR) 0Xf508406
PIO Open Drain Control Register (XPIOOD) 0Xf50C406
AC-Link Controller407
Features407
Configuration408
Functional Description409
CODEC Connection409
Boot Configuration410
Usage Flow411
AC-Link Start up413
CODEC Register Access414
Sample-Data Transmission and Reception415
GPIO Operation420
Interrupt421
AC-Link Low-Power Mode421
Registers422
ACLC Control Enable Register 0Xf700423
ACLC Control Disable Register 0Xf704426
ACLC CODEC Register Access Register 0Xf708428
ACLC Interrupt Status Register 0Xf710429
ACLC Interrupt Masked Status Register 0Xf714431
ACLC Interrupt Enable Register 0Xf718431
ACLC Interrupt Disable Register 0Xf71C431
ACLC Semaphore Register 0Xf720432
ACLC GPI Data Register 0Xf740433
ACLC GPO Data Register 0Xf744434
ACLC Slot Enable Register 0Xf748435
ACLC Slot Disable Register 0Xf74C437
ACLC FIFO Status Register 0Xf750438
ACLC DMA Channel Selection Register 0Xf784441
ACLC Audio PCM Output Data Register 0Xf7A0442
ACLC Center Data Register 0Xf7A8443
ACLC Audio PCM Input Data Register 0Xf7B0444
ACLC Modem Input Data Register 0Xf7Bc445
ACLC Revision ID Register 0Xf7Fc446
Interrupt Controller447
Characteristics447
Block Diagram448
Detailed Explanation450
Interrupt Sources450
Interrupt Request Detection451
Interrupt Level Assigning451
Interrupt Priority Assigning452
Interrupt Notification453
Clearing Interrupt Requests453
Interrupt Requests454
Registers456
Interrupt Detection Enable Register (IRDEN) 0Xf600457
Interrupt Detection Mode Register 0 (IRDM0) 0Xf604458
Interrupt Detection Mode Register 1 (IRDM1) 0Xf608460
Interrupt Level Register 0 (IRLVL0) 0Xf610463
Interrupt Level Register (IRLVL1) 0Xf614465
Interrupt Level Register 2 (IRLVL2) 0Xf618467
Interrupt Level Register 3 (IRLVL3) 0Xf61C468
Interrupt Level Register 4 (IRLVL4) 0Xf620470
Interrupt Level Register 5 (IRLVL5) 0Xf624472
Interrupt Level Register 6 (IRLVL6) 0Xf628474
Interrupt Level Register 7 (IRLVL7) 0Xf62C476
Interrupt Mask Level Register (IRMSK) 0Xf640478
Interrupt Edge Detection Clear Register (IREDC) 0Xf660479
Interrupt Pending Register (IRPND) 0Xf680480
Interrupt Current Status Register (IRCS) 0Xf6A0483
Interrupt Request Flag Register 0 (IRFLAG0) 0Xf510486
Interrupt Request Flag Register 1 (IRFLAG1) 0Xf514486
Interrupt Request Polarity Control Register (IRPOL) 0Xf518487
Interrupt Request Control Register (IRRCNT) 0Xf51C488
Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0Xf520489
Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0Xf524490
Removed491
Removed495
Removed497
Extended EJTAG Interface499
JTAG Boundary Scan Test500
JTAG Controller and Register500
Instruction Register501
Boundary Scan Register501
Device ID Register504
Initializing the Extended EJTAG Interface505
Absolute Maximum Rating (*1)507
Recommended Operating Conditions507
DC Characteristics of Pins Other than PCI Interface Pins508
DC Characteristics of PCI Interface Pins509
PLL Power510
PLL Power Connection Example510
AC Characteristics511
MASTERCLK AC Characteristics511
Power on AC Characteristics511
SDRAM Interface AC Characteristics512
External Bus Interface AC Characteristics514
PCI Interface AC Characteristics (66 Mhz)515
PCI Interface AC Characteristics (33 Mhz)515
PCI EEPROM Interface AC Characteristics517
DMA Interface AC Characteristics517
Interrupt Interface AC Characteristics518
SIO Interface AC Characteristics519
Timer Interface AC Characteristics519
PIO Interface AC Characteristics520
AC-Link Interface AC Characteristics520
Pinout and Package Information521
Pinout Diagram521
Package Dimensions529
Notes on Use of TMPR4937531
Notes on TX49/H3 Core531
Notes on External Bus Controller533
Notes on DMA Controller533
Note on PCI Controller536
Notes on Serial I/O Port540
Parts Number When Ordering541
Appendix Atx49/H3 Core Supplement543
Processor ID543
Interrupts543
Bus Snoop543
Halt/Doze Mode543
Memory Access Order543

Brand	Toshiba
Model	TX49 TMPR4937
Category	Computer Hardware
Language	English

Toshiba TX49 TMPR4937 - User Manual

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Toshiba TX49 TMPR4937 Specifications

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