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Lists various application areas where the TE0720 module can be utilized.
Highlights the main industrial-grade and rugged features of the Xilinx Zynq-7000 based SoM.
Details the default bootloader, U-Boot, and Linux preloaded on the SPI Flash.
Describes the role of the First Stage Bootloader in initializing the Zynq system and loading subsequent stages.
Explains the function of the Second Stage Bootloader, typically U-Boot, for loading the operating system.
Details the various boot modes supported by the Zynq-7000, selected via BOOT_MODE pins.
Provides steps to update SPI Flash using U-Boot commands and an SD card.
Details how to update SPI Flash via Ethernet using TFTP and U-Boot commands.
Explains using Xilinx Impact or ChipScope for loading bitstreams via JTAG.
Details how to configure the FPGA using the PS DEVCFG interface with specific binary bitstream requirements.
Shows how to configure or reconfigure the FPGA directly from the U-Boot prompt.
Provides a high-level block diagram of the TE0720 Zynq SoM and its components.
Introduces the SC (Lattice XO2-1200 CPLD) and its role in power sequencing and configuration.
Discusses options for customizing SC functions via requests or user code.
Lists the SC connections to the Board-to-Board (B2B) pins and their functions.
Explains the function and usage of the NOSEQ pin for power sequencing control.
Details the high-performance DC-DC converters used for the module's power rails.
Explains the special power sequencing requirements of Zynq devices and how the TE0720 handles them.
Lists and describes the various power rails, their input/output, and ratings.
Shows an example power connection diagram for a dual supply application.
Presents AC performance metrics in MHz for the ZYNQ PS and PL subsystems.
Lists DC characteristics, including power input pins and maximum current ratings.
Discusses how the SC can initiate software-forced resets for the Zynq.
Describes how on-board peripherals have separate reset inputs controlled by the SC.
Guides on setting up the DDR3 configuration in the Zynq environment.
Lists available manufacturer documentation for DDR3 SDRAM.
Provides steps for formatting the internal eMMC card using Linux commands.
Introduces the Marvell Alaska Gigabit Ethernet PHY used on the TE0720 and its interface.
Mentions the built-in Cable Diagnostic Feature and VCT available on Marvell Alaska PHY.
Explains how to configure fiber-copper auto-detection for the Ethernet PHY.
Discusses advanced features like PTP and SyncE supported by Marvell Alaska PHY.
Shows how to read the temperature sensor value using u-boot.
Describes the default LED settings of the Marvell PHY upon power up.
Provides a demo design for mapping PHY LEDs to user I/O signals.
Introduces the three on-board LEDs and their default connections and mappings.
Explains the mapping and availability of the green LED1.
Describes the function of the red LED2 as a global status indicator.
Details the green LED3's connection to the FPGA Done pin and its indication of FPGA configuration status.
Provides a table of LED combinations and their corresponding error or status descriptions.
Explains the programming methods for the TE0720's SPI Flash memory using Xilinx tools.
Details the configuration options for MIO pins in Bank 0, mapping them to Zynq PS Peripherals.
Shows how to use U-Boot as an I2C test tool to scan for connected devices.
Lists the shock and vibration ratings for the module's connectors.
Provides links to manufacturer documentation for the board-to-board connectors.
Details the pinout for the left connector of the TE0720 module.
Details the pinout for the top connector of the TE0720 module.
Details the pinout for the bottom connector of the TE0720 module.
Specifies the physical dimensions of the TE0720 module, including size and PCB thickness.
Lists the operating temperature ranges for commercial and industrial grade modules.
Provides the weight of the module with and without bolts.
Introduces the TE0701 Carrier Board and its documentation.
Explains how to program the FMC_VADJ voltage on the TE0701 via I2C.
Lists the functions available when using the TE0720 with the TE0603 carrier.
Provides a checklist for verifying the schematic design of a carrier board.
Offers a checklist for ensuring proper PCB layout and component placement for carrier boards.
Recommends visual checks for correct module placement on carrier boards.
Outlines the standard Zynq boot sequence followed by reference projects.
Highlights changes and potential issues with the FSBL generated by Vivado 2013.4.
Explains how to obtain and set up the necessary toolchain for building software.
Details the steps for configuring the CentOS guest OS, including installing packages and VMware tools.
Instructions for configuring virtual machine settings, specifically folder sharing.
Instructions for cloning the U-Boot source code repository.
Provides commands to build the U-Boot binary for specific module versions.
Guides on cloning the Linux kernel source code repository.
Provides commands to build the Linux kernel image and device tree blob.
Lists the required files for booting the Zynq from an SD memory card.
Explains the process of initializing and booting from the on-board QSPI Flash memory.
Introduces video and step-by-step tutorials for creating Vivado projects.
Refers to a video tutorial for Vivado 2013.2.
Refers to a step-by-step tutorial for Vivado 2013.3.
Instructions on creating a new block design and naming it.
Guides on adding IP cores, specifically the ZYNQ7 Processing System.
Guides on debugging the "Hello World" project using SDK.
Refers to a video tutorial for debugging the "Hello World" project.
Provides step-by-step instructions for debugging the "Hello World" project in SDK.
Guides on using the Xilinx Linux kernel repository specifically with the TE0720 module.
Mentions the standard Xilinx FSBL used with Petalinux and its customization.
Explains how MAC addresses are read from EEPROM and handled during the boot process.
Refers to older instructions for building projects and FSBL.
Provides general precautions for handling and using the module safely, including ESD protection.
Details the procedure for safely removing the module from a carrier board, emphasizing connector care.
Describes a specific problem encountered with FSBL and JTAG access after SPI flash programming.
Standard disclaimer regarding the document's content and accuracy.
Standard limitation of liability clause for the document's use.
Standard copyright notice for the manual.
Mentions that hardware/firmware/software is licensed.
States Trenz Electronic's commitment to environmental protection.
General| Manufacturer | Trenz Electronic |
|---|---|
| Model | TE0720 |
| Category | Control Unit |
| FPGA | Yes |
| FPGA Family | Xilinx Zynq-7000 |
| Processor | Dual-core ARM Cortex-A9 |
| SDRAM | 1 GB |
| Flash Memory | 16 MB |
| Ethernet | 10/100/1000 Mbps |
| USB | USB 2.0 |
| USB Transceiver | Yes |
| Dimensions | 100 mm x 80 mm |
| I/O Interfaces | UART, SPI, I2C |
| GPIO | 54 |
| Clocking | 33.333 MHz |
| Power Supply | 5V |
| Memory | 1 GB DDR3L SDRAM |
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