Slow Start Logic
The slow start facility causes the load current to ramp up slowly from zero when enabled and to
ramp slowly back down to zero when disabled. The speed of the ramps is determined by the slew
rate settings. A slow start is triggered when both the input enable signal IEN is asserted and the
user's voltage applied to the terminals of the load is above the threshold set by the drop-out
voltage control. This over-rides the normal operation of the Low-Voltage Drop-out circuit, so
when SST is asserted the output of IC56-C is low and Q13 is turned on pulling SSH up to +5V.
This turns off Q10 in the low voltage drop-out circuit, preventing its normal operation.
When slow start is engaged, SST is high and IC51-B gives control of the STRT signal to the
combination of IEN and the output of the slow start threshold comparator IC46-B. When STRT is
low, the level select logic sets the input to the slew rate generator to zero.
A slow start is initiated by the last of IEN being asserted high and comparator IC46-b determining
that the applied voltage (as sensed by VS) is above the drop-out threshold DROPV. At this time,
the output of IC51-A goes low and the output of IC51-B high, asserting STRT. This changes the
routing in the level select logic from 0V to the selected level signal, which passes to the slew
rate generator which starts to ramp up to the required operating level.
If both slow start and transient mode are engaged, ST is low and STRT is gated with IEN in IC56-
D and IC57-A to assert OSCGO to start the oscillator synchronously with the start of the ramp.
This ensures that the first cycle of the oscillator has the correct period, including the initial ramp-
up time.
When either IEN is negated, or the applied voltage falls below the DROPV threshold, then STRT
is negated, causing the level select logic to switch to 0V and starting the slow-stop ramp-down.
The load FETs must remain active during this ramp-down, so DRIVE must remain asserted. This
is achieved by the drive latch IC57-C & -D remaining set until the comparator IC53-C determines
that DMD has fallen nearly to zero. At this point both inputs of IC52-C are low and its output goes
high resetting the drive latch IC57-C & -D.
Fault Latch
There are six possible fault conditions detected by various comparators:
• Excessive temperature, detected by IC53-A and two Positive Temperature Coefficient
thermistors mounted on the heatsinks. This will only occur if the airflow is obstructed, or if
one of the fans fails, as otherwise the power limit will trip first.
• Excessive voltage (over about 96V) applied to the load terminals, detected by IC46-D.
• Excessive difference (over about 8V) between the external and internal sense voltages,
detected by IC46-A.
• Excessive current (over about 52A) in either load FET, detected by IC31-A & -D.
• Excessive power in the load FETs (over about 350W), detected by the power limit
multiplier and IC58-A.
• A change in the setting of the Operating Mode switch while the load is Enabled, detected by
IC49 and Q3 (which is triggered by the break-before-make action of the switch).
If any of these conditions occurs, the wired-OR active low FAULT signal is pulled down by the
open collector comparator. This forces pin 11 of IC51-D to go high and causes IC52-D to negate
DRIVE, so the output enable circuit stops the load conducting current. This state is latched by
the fault latch IC51-C & -D, and persists even if the FAULT signal is removed. IC33-D drives the
RED signal to the front panel lamp.
The fault latch can only be reset by the negation of IEN (and the completion of the slow stop
ramp-down), which makes pin 9 of IC51-C go low and pin 8 high. If the FAULT signal is no longer
present, both inputs of IC51-D are now high and its output goes low, re-enabling the path through
IC52-D from the drive latch to DRIVE.
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