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Vector 4 - Page 203

Vector 4
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0
T
med—dy
g2
RESET
(3)
T
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27018
I
g
éfi.‘
o
T4Lsop
ba
785574
S5O
uao
8088-2
(1)
CLOCK
19icLk
U130
RS53,100
”
RESET
OlyLp
A
A
iHoLo
(1)
BUSAK
,
6
17
Vi)
<
3
SaEnE
ol
(3
NN
-—5-{
S0
NM
|
gL
s
7y
L
U103
88
ENBL
(1)
ny
74tsos
(3)
INT
—1{>ofi—’§m
TR
SO
ENBL
(1)
74LS04
ISTOR
VALUES
ARE
IN
OHMS
,1/4W,
57,
ACITOR
VALUES
ARE
IN
MICROFARADS.
LESS
CTHERWISE
SPECIFIED:
An
additional
flip-flop
(U131)
and
an
AND
gate
(U103)
have
been
added.
resulted
in
a
modification
to
the
circuitry
which
controls
the
switehing
of
the
CPUs.
The
CLOCK
signal
now
clocks
the
new
FF
which
generates
the
signal
(Q)
that
is
used
to
enable
the
8088-2
(through
pin
31-HOLD).
The
88ENBL|
signal
is
pulled
from
the
8088-2s
HLD
A
line
(pin
30).
shown
on
the
cut-out
of
the
schematic.
Other
changes
are
This
has