Vector 4 - Page 212

EXHIBIT VI-3 (B) TIMING DIAGRAM FOR SBC
PEY
T
VIDEO CYCLE
o e
15.3ns
]
30.637ns
CPU CYCLE
1L L L L LT
L L 52 m (u12/6)
U 1 16 M (u115/14)
I s m (u11s/13)
1
L i L [ I ; - | L 4 M (U115/12)
1 “ l - L \ B L 2 M (U115/11)
1L SR [ 1 ‘i r_\_ LATCH (U115/15)
‘ | - w
3 L: {‘ [ ’__— CPU/VID (U107/8) CPU/VID (U107/9)
3 ‘ |.;___r ’, ' LATCHO (U89/3)
= & ; o ‘ ‘ LATCHI (U89/6)
’ L ‘ g | ‘ | } L | ; MHIGH (U69/5) MHIGH (U69/6)
L “ ' J — lf{ I RAS (U71/9)
|
-
£
L
CPU
CAS
(At
RAM
Pin
5)
3
nl
.
I
g
VID
CAS
(At
RAM
Pin
5)
i - ‘ L CLKST (U89/8)
m T LT L LI L L l__l_— CK (108/9)
___J_—_—l_____l_—l_____f—_—[ _J——_L____l_—_\___._l_ CLOCK Z80 (U1/6)
m T L____r——_;—_—l____f_—_m— ] CLOCK 8088 (U40/19)
| :
Vvl A-9