Vector 4 - Page 214

EXHIBIT VI-5 (A) INTERLEAVING WAIT STATES
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P leMuuMREQ, RD go LOW on the.falling. edge..for..a mm or a M_eQO_B.gm Cycle.., In a Fetch the Address is put on Address Bus at beginning of Tj.
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a1’!‘2 For an ILQ Cycle RD, WR; and IORQ go LOW just y&t nsxg\g edge. qu a M_emgm__mm Cycle the WR goes LOW on the falling edge.
T3 For a Eg_u;h Cycle the Data Bus is sampled during the rising edge. For a Memory Read the Data Bus is sampled just past the falling edge. For a
- . o -Write -the ‘Data Bus-holds -stable-data {WR -is LOW) from-falling- edge .of ~ Tg'to just past falling edge-of T3. For an /Q Write the Data Bus holds sta
(WR is LOW) from the last 1/4 of T; to the 1/2 clock period of T3. ;
% ° Other TPV’ samplés WAIT dufing the faHing edge OF' Ty and otfher Twe ,
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* For further mformatlon see the ZILOG ZBO—@PU, zsoArcpu‘ TECHNICAL MANUAL.
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The éxhlblf on ;he ‘next page shows how two Z80B mstructlons (LD r, s and DJINZ, given. The top description ( “s"s"a"s"s"s""s"s"s"s" ) descrlbes the SBC logic activity
e) are lmplemented through the usg~ ‘of WAIT States.* The exhibit is divided into from the CPU standpoint. The bottom description ( r:::iiisiii: W) describes the
four gcomplete computer phases with ‘each tomputer phase having flve T States and SBC loglc activity from the VIDEO standpoint. :
two cycles: VIDEO and CPU. These cycles remaln f:xed even thoug‘h the *
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¢ This exhibit gives the ideal timing for the CPU/VID signals. The liming diagram
The following diagram shows the four complete phases. Under each computer phase . in Exhibit VI-3 shows the typical timing (including delays) for the CPU/VID signals
a description of the loglc actmty for the respectlve T States of that cycle are and all other major SBC signals.
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VIDEO Cycle ! CPU Cycle
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Phase 1
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——— Phase 2 .
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Phase 3 '
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