Vector 4 - Page 215

- - -
v i i v
1
|
.
©
,
o,
EXHIBIT
VI-5
(B)
INTERLEAVING
WAIT
STATES
e
)
v
.
T
e
i
KEY
.
DINZ,e
M1
with
5
T
States
(OP
Code
Fetch).
M2
with
3
T
States
“
INSTRUCTION
NOTE
(Memory
data
Read)
and
a
M3
cycle
with
5
T
States
(Internal
*
R
CPU
‘operations).
"
;
LD
r,s
Ml
with
f
T
States
(OP
Code
Fetch)
1
VIDEO CYCLE | CPU CYCLE
cru/vo | %
! ® -
I
)
Ty
Tg
t
Tw
*
Tw
. Microprdcessor ‘address goes from CPU/VIDEO Address MUX to Dynamic RAM. Data is released from
Microprocessor Address goes from _ RAM and sent to CPU MUX Latch.
Microprocessor through Microprocessor
MUX to CPU/VIDEO Address MUX. (1)
Video address goes from Video Controller to Video MUX to CPU/VIDEO Address MUX. An 8-bit value
is released from LSB Video MUX Latch (U58) and routed to the Character Generators. The resulting
3
16-bit value is sent to the Alpha Mode Shift Registers. (2) '
= £ -
‘ 3
- o wonk
A . - - -
; . i |
e
o
——T——
! T A . - :
T3
‘
T4
T,
|
™
Ty
Tw
Data is released from CPU MUX Latch and READ by microprocessor. Microprocessor Address Microprocessor address goes from CPU/VIDEO Address MUX to Dynamic RAM. Data is released from
: goes from microprocessor || RAM and sent to' CPU MUX Latch,
3 to CPU/VIDEO r\ddress o -
1 MUX. -
;
F
Video Address goes from CPU/VIDEO Address MUX to Dynamic RAM. Data (16 bits) is released and |y - . : e
is sent to two V}feo MUX Latches (<C35) (3). An 8-bit value is routed from MSB Video MUX Llatch Video address goes from Video Controller to Video MUX to CPU/VIDEO Address MUX. An 8-bit value
(US7)
to
the
Character
Generators.
The
resulting
16-bit
value
is
sent
to
the
Alpha
Mode
Hhift
is
released
from
LSB
Video;MUX:
Latch
(U58)
and
routed
to
the
Character
Generators.
The
resulting
Registers. 1 i || 16-bit value is sent to the Alpha Mode Shift Registers. (2)
i
i ~ - .- -
I T3 * T4 Ts T1 ' T2
i
L | Data is relessed from CPU MUX Latch and READ by microprocessor. , J‘ Mieroprocessor “address ‘goes from CPU/VIDEO Address MUX to Dynamic RAM.
I - * = ! Data.-is-released from RAM and sent to CPU MUX Latch.
‘ . . ., oL o, T S " - ¢
£ - T ® v Bl
Video Address goes from CPU/VIDEO Address MUX to Dynamic RAM. Data (16 bits) is released and 1t — _ —— - — ;
is sent to two Video MUX Latches (<C3Y) (3). An 8-bit value is routed from MSB Video MUX Lptch Video address goés from Video Controller to Video MUX to CPU/VIDEO Address MUX. An 8-bit value
(US7) to the Charhcter Generators., The resulting 16-bit value is sent to the Alpha Mode $hift is released from LSB_Video MUX Latch (U58) and routed to the Character Generators. The resulting
Registers. , 16-bit value is sent to the Alpha Mode Shift Registers. (2)
1
% 2 < i
1 { ' o . X x
T3 | T1 T2 0 e T3 . = { T4
Data
is
released
from
CPU
MUX
[
Internal
microprocessor
operations.
3
d
‘
'
.A
"t
Latch and READ by eree pera’o SN - _ - D
microprocessor. ! . - g o~
Yideo
Address
go}és
from
CPU/VIDEO
Address
MUX
to
Dynamic
RAM.
Data
(16
bits)
is
released
and
(1)
The
Z80B
mode
requires
the
address
to,
go
through
the;
Address.
Mapping
RAM
Subsystem
(<B1>),
is
sent
to
two
Video
MUX
Latches
(<C3>)
(3).
An
8-bit
value
is
routed
from
MSB
Video
MUX
Llatch
(2)
The
MSB
is
physically
displayed
on
the
screen.
(US7)
to
the
Char?cter
Generators.
The
resulting
16-bit
value
is
sent
to
the
Alpha
Mode
phift
(3)
For
Alpha
Video
Mode.
Registers.
(4)
This
is
followed
by
a
Ts5
State
within
the
Video
Cyecle.
i
—
VI A-12
2
o
e